Run-Length Mapping Table for Flash Memory Address Translation
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Solution Overview
Problem
Existing data storage devices face challenges in minimizing the size of the address translation layer mapping table, which is necessary for efficient data access and defect management in non-volatile semiconductor memories, as it requires significant volatile memory resources.
Innovation Solution
Implementing a run-length mapping table (RLMT) and a single address mapping table (SAMT) to dynamically create and coalesce entries based on the number of consecutive memory segments accessed, optimizing the mapping process to reduce the size of the mapping table and facilitate efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a traditional address translation layer maps every LBA to PBA individually, then mapping accuracy is improved, but volatile memory size requirements increase significantly
Solution Approach 1:
The patent divides the address translation layer into two distinct mapping tables: a run-length mapping table (RLMT) that handles sequential address ranges using compact run-length encoding, and a single address mapping table (SAMT) that handles individual address mappings. This segmentation allows the system to use efficient compact representations for sequential accesses while maintaining full mapping capability for random accesses, thereby reducing overall volatile memory requirements while preserving mapping accuracy.
Solution Approach 2:
The patent changes the representation parameters of the mapping data by introducing run-length encoding for sequential address ranges. Instead of storing individual (LBA, PBA) pairs for consecutive addresses, the system stores a starting address and a run length, fundamentally changing how sequential mappings are parameterized. This parameter transformation dramatically reduces the memory footprint for sequential address translations while maintaining complete mapping information.
2Quantity of substance
If the mapping table size is reduced to minimize volatile memory, then memory cost is reduced, but mapping completeness may be compromised
Solution Approach 1:
The patent implements a dynamic mapping system where the choice between RLMT and SAMT depends on the access pattern. Sequential address ranges are dynamically encoded in the compact RLMT format, while individual or non-sequential addresses use the detailed SAMT format. This dynamic adaptation ensures that the mapping table remains complete and accurate for all access types while optimizing memory usage based on the specific mapping requirements of each address range.
Solution Approach 2:
The patent merges two different mapping approaches (run-length encoding for sequences and individual address mapping) into a unified address translation system. The RLMT and SAMT work together complementarily, with the RLMT handling bulk sequential mappings efficiently and the SAMT handling individual or irregular mappings with full detail. This combination ensures mapping completeness across all access patterns while achieving significant memory reduction through the RLMT's compact representation.
Data Source
AI summary
A data storage device is disclosed comprising a non-volatile memory comprising a plurality of memory segments. When a write command comprising a logical block address (LBA) is received, a number of consecutive memory segments to access in response to the write command is determined. When the number of consecutive memory segments to access is greater than a threshold, a new run-length mapping entry in a run-length mapping table (RLMT) is created. When the number of memory segments to access is not greater than a threshold, at least one new single address mapping entry in a single address mapping table (SAMT) is created.