Run-Level Address Mapping Table for Flash Memory
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Solution Overview
Problem
Conventional address mapping methods for flash memory, such as page-level and block-level mapping, face challenges in managing increasing data storage capacities, leading to larger address mapping tables and inefficiencies, particularly in managing address mapping information with expanding host device memory capacities.
Innovation Solution
The implementation of a run-level address mapping table that stores initial and total size values for consecutive physical addresses, allowing for efficient mapping using a small memory capacity, and employing a copy-back operation to accurately determine offset values and compactly store data, thereby reducing memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If page-level address mapping is used, then address mapping accuracy is improved, but memory capacity requirement increases
Solution Approach 1:
The patent divides the address mapping table into multiple segments or levels (first address mapping table and second address mapping table). The first table stores a subset of address mappings, while the second table stores additional mappings. This segmentation allows the system to maintain high address mapping accuracy while distributing the memory storage requirement across multiple smaller tables, thereby reducing the memory capacity requirement for any single table.
Solution Approach 2:
The patent introduces a hierarchical or multi-dimensional structure for address mapping by organizing mappings across multiple tables with different scopes or granularities. Instead of a single flat table, the system uses a layered approach where the first table handles primary mappings and the second table handles secondary or extended mappings, effectively adding a dimensional layer to the address mapping structure that optimizes both accuracy and memory efficiency.
2Quantity of substance
If block-level address mapping is used, then memory capacity requirement is reduced, but device complexity increases
Solution Approach 1:
The patent segments the address mapping management into distinct functional components: a first address mapping table for primary mappings and a second address mapping table for additional mappings. This segmentation simplifies the management complexity by allowing each table to be handled independently with clearly defined roles, rather than managing a single complex table that would require handling both primary and secondary mappings simultaneously.
Solution Approach 2:
The patent introduces an intermediary mechanism (the second address mapping table) that mediates between the limited first address mapping table and the full address space requirements. This intermediary table handles the additional mappings that cannot be accommodated in the first table, thereby reducing the complexity of the primary mapping table while still providing comprehensive address mapping coverage.
3Adaptability or versatility
If log-block scheme with multiple mapping tables is used, then address mapping flexibility is improved, but device complexity increases
Solution Approach 1:
The patent merges the functionality of multiple address mapping tables into a coordinated two-table system where the first and second tables work together as an integrated unit. Rather than managing separate mapping tables for different purposes (as in log-block schemes), this merged approach consolidates address mapping operations into a unified structure that maintains flexibility while reducing control complexity through standardized access procedures.
Solution Approach 2:
The patent creates a universal address mapping structure where the two-table system can handle various types of address mapping requirements (primary mappings, extended mappings, and additional mappings) through a single standardized mechanism. This multi-functional design provides the adaptability and versatility of multiple specialized tables while using a unified control approach that reduces overall device complexity.
Data Source
AI summary
A run level address mapping table and related method provides for storing address mapping data, which maps logical addresses to physical addresses in a flash memory using a flash translation layer. A first value is stored in the address mapping table, indicating an initial location for a run within a memory block, the run having at least two consecutive physical addresses. A second value is stored in the address mapping table, indicating a total size for the run.