Run-Time Configurable Architecture Scheduler for Dynamic Resource Allocation
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Solution Overview
Problem
Conventional computing architectures, such as CPUs, are inefficient in handling modern algorithms due to architectural limitations, leading to the need for specialized ASICs or FPGAs, which are costly, time-consuming to develop, and inflexible for repurposing as algorithms advance.
Innovation Solution
A scheduler-based compiler system for reconfigurable architectures that dynamically allocates hardware resources across multiple programs and functions, allowing for spatial and temporal multiplexing, resource prioritization, and avoidance of defective resources, enabling efficient execution of multiple functions simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional CPUs are used for computing, then general-purpose functionality is maintained, but performance efficiency for modern algorithms deteriorates
Solution Approach 1:
The patent implements a dynamic reconfiguration system where the hardware architecture can be dynamically changed at runtime based on the computational task. The reconfigurable array allows functional units to be dynamically added, removed, or modified without physical hardware changes, enabling the system to adapt to different algorithms while maintaining high performance.
Solution Approach 2:
The reconfigurable array serves multiple functions by allowing the same physical hardware to be reconfigured for different computational tasks. A single array can implement various algorithms (e.g., matrix multiplication, convolution, graph processing) by changing the connectivity and functional configuration, eliminating the need for separate dedicated hardware for each function.
2Productivity
If specialized ASICs are developed for each algorithm, then computational performance is optimized, but development time and cost increase
Solution Approach 1:
The system provides a library of pre-defined functional units and reconfiguration templates that can be selected and combined to create custom algorithms. Instead of designing ASICs from scratch, developers can use pre-built blocks (e.g., multiply-accumulate units, memory interfaces) and pre-configured connection patterns, significantly reducing development time while maintaining performance optimization.
Solution Approach 2:
The patent enables performance optimization through parameter changes in the reconfiguration process. Developers can adjust parameters such as the number of functional units, data precision, memory bandwidth, and connectivity patterns to match the specific requirements of each algorithm, achieving ASIC-level performance without the development complexity.
3Adaptability or versatility
If FPGA-based implementations are used, then development flexibility is improved, but performance throughput and power efficiency deteriorate
Solution Approach 1:
The reconfigurable array is segmented into multiple independently controllable functional units that can be activated or deactivated based on the computational task. This segmentation allows the system to achieve high throughput by activating only the necessary units for a given algorithm, reducing power consumption and improving efficiency compared to fully parallel FPGA implementations.
Solution Approach 2:
The patent uses virtualization techniques where multiple virtual instances of functional units are created within the reconfigurable array. These virtual copies can be dynamically allocated and migrated between physical hardware resources, enabling high throughput workloads while maintaining the flexibility to reconfigure for different algorithms without the overhead of multiple physical FPGAs.
4Adaptability or versatility
If multiple ASICs are deployed in a system, then specific computational tasks can be performed, but system complexity and cost increase
Solution Approach 1:
The patent merges the functionality of multiple separate ASICs into a single reconfigurable array. Instead of having separate hardware blocks for different computational tasks, the system combines all possible functions into one unified platform that can be reconfigured to perform any of the tasks as needed, significantly reducing system complexity while maintaining full computational capability.
Solution Approach 2:
The reconfigurable array serves as a universal computing platform that can replace multiple specialized ASICs. By configuring the array differently, the same hardware can perform matrix operations, signal processing, graph algorithms, or other computational tasks, eliminating the need for multiple dedicated hardware components and simplifying the overall system architecture.
Data Source
AI summary
Systems and method for scheduler architectures that can enable reconfigurable architecture to execute multiple functions in accordance with embodiments of the invention are described. An embodiment includes a compiler system for reconfiguration of compute resources, including: a scheduler, a reconfigurable architecture array including several a hardware resources, where the schedular dynamically reconfigures the reconfigurable architecture array by: determining several programs including a first program and a second program that require execution on the reconfigurable architecture array at a particular time n, wherein each program includes several function, and determining hardware resources required by the first program and the second program; allocate a set of functions from the several functions of the first program and the second program to different hardware resources from the several hardware resources of the reconfigurable architecture array based on the determined hardware resources required by the first program and the second program.