Run-Time Consistency Check for Non-Sequential Instruction Fetches
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Solution Overview
Problem
Conventional control flow checking methods in processors are inefficient in detecting errors in non-sequential instruction executions, particularly in packed processor architectures, as they often require additional instructions or dedicated bits, which can reduce the information stored in instructions and are not robust enough to handle hardware and software errors effectively.
Innovation Solution
The proposed solution involves an instruction set architecture with run-time consistency check that uses multiple encodings for instructions, where instructions targeted for non-sequential fetch operations are encoded with specific numerical properties (like parity) to detect errors and prevent execution of incorrect instructions, employing a consistency check module and bitwise XOR networks to validate parity and trigger appropriate actions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional control flow checking methods are used, then the processor can execute instructions, but error detection capability in non-sequential instruction executions is insufficient
Solution Approach 1:
The patent changes the numerical parameter (parity bit) of instruction encodings based on whether they are targets of non-sequential fetch operations. Instructions that are targets of non-sequential fetches are encoded with a first numerical property value, while other instructions use a second numerical property value. This parameter differentiation enables error detection without requiring additional hardware complexity.
Solution Approach 2:
The patent performs preliminary encoding of instructions with appropriate numerical property values before execution. The system pre-identifies which instructions are targets of non-sequential fetch operations and assigns them specific parity values. This preliminary preparation enables runtime error detection without adding complexity to the execution phase.
2Reliability
If additional instructions or dedicated bits are added for error detection, then error detection capability improves, but the information stored in instructions is reduced
Solution Approach 1:
The patent utilizes existing instruction encoding parameters (parity bits) and changes their interpretation based on the instruction's role. By differentiating numerical property values for target instructions versus other instructions, the system achieves error detection without adding extra bits or reducing the information capacity of existing instruction fields.
Solution Approach 2:
The patent makes the existing instruction encoding system multi-functional by using the same instruction fields for both information storage and error detection purposes. The numerical property values serve dual roles: encoding instruction information and providing error detection capability, eliminating the need for separate dedicated error detection bits.
3Reliability
If numerical property values are used to detect errors in non-sequential fetch operations, then run-time error detection is achieved, but the system complexity increases
Solution Approach 1:
The patent implements a self-service error detection mechanism where the instruction encoding itself provides the detection capability. The numerical property values embedded in the instruction encodings enable the system to self-validate without requiring complex external checking mechanisms. The processor naturally encounters these parity values during normal instruction fetch and execution.
Solution Approach 2:
The system provides feedback by comparing the actual numerical property value of fetched instructions against expected values. When a non-sequential fetch occurs, the system checks whether the fetched instruction has the correct first numerical property value, providing runtime feedback on instruction integrity without complex additional hardware.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of processor operations by robustly detecting hardware and software errors at run-time, reducing the likelihood of executing incorrect instructions and preventing data corruption or crashes, without reducing the information stored in instructions.
Implementation Method 1
determine whether an instruction is a target of a non-sequential fetch operation with an expected numerical property value
Implementation Method 2
employing a consistency check module and bitwise XOR networks to validate parity
Data Source
AI summary
A system and method includes modules for determining whether an instruction is a target of a non-sequential fetch operation with an expected numerical property value, and avoiding execution of the instruction if it is the target of the non-sequential fetch operation and does not have the expected numerical property. Other embodiments include encoding an instruction with a functionality that is a target of a non-sequential fetch operation with an expected numerical property value. Instructions with the same functionality that are not targets of non-sequential fetch operations can be encoded with a different numerical property value. More specific embodiments can include a numerical property of parity, determining whether the instruction is valid, and throwing an exception, setting status bits, sending an interrupt to a control processor, and a combination thereof to avoid execution.