Run-Time Controller for Electronic Circuits Managing Process Variations
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Solution Overview
Problem
Deep submicron technologies face significant challenges with process variability, leading to performance degradation and increased energy consumption in digital circuits, particularly in memories, due to unpredictable variations in IC parameters such as threshold voltage and resistance, which current design methodologies struggle to address effectively.
Innovation Solution
The proposed solution involves a design-time run-time separation approach, where circuit design allows for run-time adaptation using a run-time controller, with pre-selected working points defined by Pareto curves that balance performance and cost parameters, enabling the system to operate optimally under varying conditions without worst-case design margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If corner-point analysis is used in design to maximize parametric yield, then reliability is improved, but device complexity and energy consumption increase
Solution Approach 1:
The patent introduces a run-time controller that dynamically selects operating points based on actual circuit behavior and process variations. Instead of using static corner-point analysis that requires multiple fixed designs, the system adapts at run-time to select the most appropriate operating point, thereby reducing design complexity while maintaining reliability.
Solution Approach 2:
The patent changes the approach from selecting among fixed corner-point designs to dynamically adjusting operating parameters at run-time. The run-time controller modifies operating conditions (such as voltage, frequency, or configuration) based on measured process variations, allowing a single design to adapt to different conditions rather than requiring multiple predetermined designs.
2Reliability
If corner-point analysis is used in design to maximize parametric yield, then reliability is improved, but energy consumption increases
Solution Approach 1:
The run-time controller dynamically selects operating points based on actual circuit performance and process variations, allowing the system to use lower energy configurations when conditions permit rather than always operating at conservative corner points. This dynamic adaptation reduces average energy consumption while maintaining reliability.
Solution Approach 2:
The system changes operating parameters at run-time to optimize energy consumption. Instead of being locked into high-energy corner-point designs, the run-time controller adjusts parameters such as voltage levels, frequency, or operational mode based on measured conditions, thereby reducing energy consumption while maintaining acceptable performance and reliability.
3Adaptability or versatility
If design-time run-time separation is implemented with run-time adaptation, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent segments the design process into distinct design-time and run-time components. At design-time, the system prepares a set of candidate operating points and the necessary control logic. At run-time, only the selection and adjustment mechanisms are activated, which are relatively simple compared to the overall system. This segmentation allows high adaptability while keeping the added complexity manageable and localized.
4Productivity
If worst-case design margins are avoided, then productivity is improved, but reliability may worsen under process variability
Solution Approach 1:
The patent implements feedback mechanisms where the run-time controller monitors actual circuit performance and process variations, then adjusts operating points accordingly. This feedback loop ensures that reliability is maintained under process variability without requiring excessive worst-case margins at design-time, thereby improving productivity while preserving reliability through adaptive correction.
Solution Approach 2:
At design-time, the system performs preliminary preparation by identifying a set of candidate operating points and the control logic needed to select among them. This preliminary action allows the design to be more aggressive (with smaller margins) while still ensuring reliability, because the run-time selection mechanism will choose appropriate operating points based on actual conditions rather than requiring all designs to accommodate worst-case scenarios.
Data Source
AI summary
Methods and apparatus are described in which, at design-time a thorough analysis and exploration is performed to represent a multi-objective “optimal” trade-off point or points, e.g. on Pareto curves, for the relevant cost (C) and constraint criteria. More formally, the trade-off points may e.g. be positions on a hyper-surface in an N-dimensional Pareto search space. The axes represent the relevant cost (C), quality cost (Q) and restriction (R) criteria. Each of these working points is determined by positions for the system operation (determined during the design-time mapping) for a selected set of decision knobs (e.g. the way data are organized in a memory hierarchy). The C-Q-R values are determined based on design-time models that then have to be “average-case” values in order to avoid a too worst-case characterization. At processing time, first a run-time BIST manager performs a functional correctness test, i.e. checks all the modules based on stored self-test sequences and “equivalence checker” hardware. All units that fail are deactivated (so that they cannot consume any power any more) and with a flag the run-time trade-off controllers, e.g. Pareto controllers, are informed that these units are not available any more for the calibration or the mapping. At processing time, also a set of representative working points are “triggered” by an on-chip trade-off calibration manager, e.g. a Pareto calibration manager, that controls a set of monitors which measure the actual C-Q-R values and that calibrates the working points to their actual values. Especially timing monitors require a careful design because correctly calibrated absolute time scales have to be monitored.


