Runahead Correlate Code Branching for Latency Event Resolution

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Solution Overview

Problem

Micro-processing systems in speculative execution mode, such as runahead, face limitations in addressing additional latency events due to the execution of code in the same manner as outside of runahead, which restricts the system's ability to efficiently handle latency events.

Innovation Solution

The system branches to alternate 'runahead correlate' code when in runahead mode, specifically designed to optimize the process by omitting or modifying instructions that do not contribute to uncovering latency events, prioritizing memory operations, and terminating runahead when it is unlikely to provide benefits, using a special instruction for condition testing and dynamic profiling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If code is executed in the same manner during runahead as outside of runahead, then the execution logic remains simple and uniform, but the system's ability to efficiently uncover and address additional latency events is limited

Engineering Contradiction:

Improveability to uncover and address latency eventsVSAvoidexecution logic complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the code into two separate versions: normal code for standard execution and runahead correlate code for speculative execution. This segmentation allows each version to be optimized for its specific purpose—the runahead correlate code can be specially structured to efficiently uncover latency events while the normal code maintains simplicity for regular execution.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different execution characteristics to different code paths. The runahead correlate code is specifically designed with properties optimized for latency event detection (such as prioritizing memory operations and omitting non-critical instructions), while the normal code maintains its standard execution characteristics. This local differentiation resolves the contradiction by providing specialized optimization only where needed.

Inventive Principle:

Principle #3Local quality

2Productivity

If all instructions are executed during runahead to maintain complete code coverage, then accuracy is preserved, but power consumption increases and time efficiency decreases

Engineering Contradiction:

Improvetime efficiency during runaheadVSAvoidpower consumption during runahead

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent extracts and removes instructions from the runahead correlate code that do not contribute to uncovering latency events. By taking out non-essential instructions (such as computations unrelated to memory operations or instructions that would not reveal additional stalls), the system reduces power consumption and execution time while maintaining the ability to detect latency events.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies partial action by executing only the subset of instructions necessary for runahead purposes rather than all instructions. The runahead correlate code performs partial execution focused specifically on latency event detection, omitting instructions that would consume power and time without contributing to the primary goal of uncovering additional stalls.

Inventive Principle:

Principle #16Partial or excessive action

3Reliability

If the system continues runahead execution even when unlikely to provide benefits, then complete latency event detection is maintained, but unnecessary power is consumed and execution time is wasted

Engineering Contradiction:

Improvelatency event detection completenessVSAvoidunnecessary power consumption

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent incorporates feedback mechanisms that monitor the progress and effectiveness of runahead execution. Based on feedback from the execution state and latency event detection results, the system can dynamically determine when to terminate runahead, avoiding continued execution when it is unlikely to yield additional benefits while maintaining reliable detection of actual latency events.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS9804854B2Branching to alternate code based on runahead determination

Publication Date: 2017.10.31 NVIDIA CORP

AI summary

The description covers a system and method for operating a micro-processing system having a runahead mode of operation. In one implementation, the method includes providing, for a first portion of code, a runahead correlate. When the first portion of code is encountered by the micro-processing system, a determination is made as to whether the system is operating in the runahead mode. If so, the system branches to the runahead correlate, which is specifically configured to identify and resolve latency events likely to occur when the first portion of code is encountered outside of runahead. Branching out of the first portion of code may also be performed based on a determination that a register is poisoned.