Runtime Programmable BIST for Multi-Port Memory Fault Detection
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Solution Overview
Problem
Testing multi-port memory devices for realistic faults is challenging due to the complexity of simulating simultaneous memory access operations, which cannot be addressed by methods used for single-port memory devices, and existing approaches are inefficient, requiring years to complete exhaustive tests and limiting the ability to adapt to new test procedures.
Innovation Solution
A programmable system with a built-in self-test (BIST) capability that generates test operations based on instruction sequences, allowing for dynamic configuration to detect multi-port memory faults, including inter-port and cell-array faults, by performing simultaneous memory access operations and adapting to new test procedures without hardware changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If exhaustive testing is performed on multi-port memory device, then fault detection coverage is improved, but test time increases to several years
Solution Approach 1:
The patent applies partial action by implementing a built-in self-test (BIST) mechanism that performs targeted testing of specific fault models rather than exhaustive testing of all possible interactions. The system selectively activates test procedures for inter-port faults and cell-array faults based on instruction sequences, achieving high fault detection coverage without requiring years of test time.
Solution Approach 2:
The patent implements self-service through a programmable BIST mechanism integrated within the multi-port memory device. The device tests itself using internal resources including scan registers, test data inputs, and fault detection logic, eliminating the need for external testing equipment and reducing test time while maintaining high fault detection coverage.
2Stability of the object's composition
If custom test procedure is hard-wired into testing apparatus, then test procedure stability is improved, but adaptability to new test procedures deteriorates
Solution Approach 1:
The patent applies dynamics by making the test procedure programmable rather than hard-wired. The BIST mechanism can be dynamically reconfigured through instruction sequences loaded into scan registers, allowing the testing apparatus to adapt to new test procedures while maintaining stable operation during execution. This enables updates to fault models and test algorithms without hardware changes.
Solution Approach 2:
The patent implements parameter changes by using programmable logic to store test procedure instructions and fault model parameters. The system can modify test behavior by changing the instruction sequences and control parameters loaded into the BIST mechanism, enabling adaptability to new test procedures while maintaining stable execution through controlled parameter management.
3Reliability
If simultaneous memory access operations are performed on two ports, then realistic fault detection is improved, but test complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the complex multi-port memory testing into separate, manageable components. The BIST mechanism is segmented into independent modules including address generators for each port, data inputs, fault detection logic for inter-port faults, and cell-array fault detection. This segmentation reduces test complexity by allowing each module to be designed and controlled independently while still achieving realistic fault detection through coordinated operation.
Data Source
AI summary
One embodiment provides a runtime programmable system which comprises methods and apparatuses for testing a multi-port memory device to detect a multi-port memory fault, in addition to typical single-port memory faults that can be activated when accessing a single port of a memory device. More specifically, the system comprises a number of mechanisms which can be configured to activate and detect any realistic fault which affects the memory device when two simultaneous memory access operations are performed. During operation, the system can receive an instruction sequence, which implements a new test procedure for testing the memory device, while the memory device is being tested. Furthermore, the system can implement a built-in self-test (BIST) solution for testing any multi-port memory device, and can generate tests targeted to a specific memory design based in part on information from the instruction sequence.