Runtime Fault Propagation Control in Digital Circuit Verification
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Solution Overview
Problem
Existing functional verification systems for digital circuits lack the flexibility to dynamically control fault propagation at runtime, requiring recompilation for changes in barriers, which is time-consuming and inefficient, especially for large SOC designs.
Innovation Solution
A method and system that allow dynamic control of fault propagation by enabling the user to selectively enable or disable fault propagation at runtime through a Unified Command Line Interface (UCLI) file or separate module, without modifying the design, thereby providing temporal control over fault functional verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dynamic control of fault propagation is implemented at runtime, then flexibility and efficiency of fault functional verification are improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic control of fault propagation by allowing barriers to be enabled or disabled at runtime during functional verification. This dynamic mechanism enables the verification system to adapt fault propagation behavior based on test requirements without recompilation, improving efficiency while managing complexity through controlled flexibility
Solution Approach 2:
The patent changes the state parameter of barriers from static (compile-time only) to dynamic (runtime controllable). By allowing barrier enable/disable states to change during verification execution, the system can efficiently adjust fault propagation characteristics without redesigning the verification methodology, thus improving productivity
2Measurement precision
If barriers are modified to control fault propagation, then accuracy of fault detection is improved, but time required for recompilation increases
Solution Approach 1:
The patent transitions from static barrier configuration requiring recompilation to dynamic barrier control that operates at runtime. This allows accurate fault detection through barrier modification without time-consuming recompilation cycles, as the verification system can adjust barrier states during execution rather than requiring redesign
Solution Approach 2:
The patent performs preliminary barrier configuration at compile-time to establish the verification framework, then allows runtime adjustment of barrier states for specific fault detection scenarios. This separation of framework setup (one-time) and scenario-specific configuration (runtime) eliminates the need for recompilation while maintaining detection accuracy
3Reliability
If fault propagation is enabled throughout the entire design, then comprehensive fault coverage is improved, but verification time increases
Solution Approach 1:
The patent segments the design into regions protected by individual barriers, allowing selective fault propagation control. Instead of enabling fault propagation throughout the entire design, the system can activate barriers to limit propagation to specific areas, maintaining comprehensive fault coverage where needed while reducing verification time in other regions
Solution Approach 2:
The patent applies partial action by enabling fault propagation only in specific regions or under specific conditions rather than universally throughout the entire design. This selective approach maintains sufficient fault coverage for critical areas while reducing overall verification time by avoiding unnecessary propagation analysis in other regions
Data Source
AI summary
A system and method for temporal control of fault functional verification. In some embodiments, a method includes: determining, in a nominal functional verification of a circuit, that an output of a first component has a first value at a first point in time, the output of the first component being connected to an input of a second component by a wire; determining, in a fault functional verification of the circuit, that the output of the first component has a second value, different from the first value, at the first point in time; determining, based on runtime input, that the wire passes through a barrier; and setting, in the fault functional verification, the value of the input of the second component, at the first point in time, to the first value.