Runtime FPGA/CGRA Reconfiguration for Vulnerable Circuit Resilience
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Solution Overview
Problem
Existing data processing circuits in safety-critical systems face challenges in resilience against transient and permanent errors, which are not adequately addressed by duplicating processing circuitry, leading to high power consumption and inefficiency, and do not protect against design errors exploitable by attackers.
Innovation Solution
A data processing apparatus that determines the vulnerability of functional circuits and modifies reprogrammable circuit behavior to match the architectural behavior of vulnerable circuits, using reprogrammable circuitry such as a field programmable gate array or coarse grained reconfigurable array, with arbitration to ensure reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processing circuitry is duplicated to enhance resilience against errors, then reliability is improved, but power consumption and circuit space increase considerably
Solution Approach 1:
The patent divides the circuit into vulnerable and non-vulnerable functional circuits, applying resilience measures only to the vulnerable segments rather than duplicating the entire processing circuitry. This selective approach reduces power consumption while maintaining reliability for critical functions.
Solution Approach 2:
The patent applies different quality levels of protection to different parts of the circuit. Vulnerable functional circuits receive enhanced protection through reprogrammable duplication, while non-vulnerable circuits operate without duplication, optimizing the balance between reliability and power consumption.
2Reliability
If processing circuitry is duplicated to enhance resilience, then reliability is improved, but circuit space increases considerably
Solution Approach 1:
The patent segments the processing circuitry into vulnerable and non-vulnerable functional circuits, duplicating only the vulnerable portions using reprogrammable logic. This reduces the overall circuit space required compared to full duplication of all processing elements.
Solution Approach 2:
The patent uses reprogrammable circuitry that can dynamically change its configuration and behavior. This allows the same physical circuit space to serve multiple functions - acting as a vulnerable functional circuit when needed and as a resilient duplicate when required, reducing the static space requirement.
3Reliability
If standard processing circuitry is used, then device complexity is low, but vulnerability to transient and permanent errors increases
Solution Approach 1:
The reprogrammable circuitry serves multiple functions: it can be configured to duplicate vulnerable functional circuits, changed to match different architectural behaviors, and used for error detection and correction. This multi-functionality reduces the need for separate dedicated circuits for each resilience function.
Solution Approach 2:
The patent changes the behavioral parameters of the reprogrammable circuitry through reconfiguration to match the architectural behavior of vulnerable functional circuits. This allows the same hardware to adapt to different vulnerability scenarios without requiring physically different circuit designs.
4Reliability
If full circuit duplication is implemented for resilience, then reliability against design errors is improved, but power consumption and circuit space increase
Solution Approach 1:
The patent identifies and segments only the vulnerable functional circuits that are susceptible to design errors, rather than duplicating all processing circuitry. This targeted approach provides protection against design errors while minimizing power consumption.
Solution Approach 2:
The patent implements partial duplication of vulnerable functional circuits using reprogrammable logic, which provides sufficient protection against design errors without the excessive resource consumption of full duplication. The reprogrammable nature allows flexible allocation of resources.
Data Source
AI summary
A data processing apparatus is provided. Determination circuitry performs a determination of a vulnerability of each of a plurality of functional circuits in a processing circuit and modification circuitry modifies a behaviour of a reprogrammable circuit to match an architectural behaviour of a vulnerable functional circuit in the functional circuits in response to the determination.