Ruthenium-Lined Copper Interconnects with Cobalt Capping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for fabricating integrated circuits with ruthenium-lined copper interconnect structures lead to the formation of galvanic cells, causing copper corrosion and time-dependent dielectric breakdown (TDDB) due to copper ion migration into the dielectric material.
Innovation Solution
The method involves recessing the copper within ruthenium-lined trenches and encapsulating it with a capping layer, such as cobalt, manganese, or dielectric material, to prevent exposure during planarization, thereby isolating copper from the dielectric material and preventing copper-ruthenium interaction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a ruthenium liner layer is deposited to line the trench before copper filling, then copper adhesion to the trench walls is enhanced, but galvanic cell formation occurs leading to copper corrosion and copper ion migration into the dielectric material
Solution Approach 1:
A cobalt-containing capping layer is deposited over the copper-containing metal to act as an intermediary barrier between the copper and the ruthenium liner layer. This prevents direct contact between copper and ruthenium, eliminating galvanic cell formation and copper ion migration, while still maintaining copper adhesion to the trench walls through the ruthenium liner.
Solution Approach 2:
The liner structure is segmented into multiple functional layers: a ruthenium-containing liner layer that provides adhesion to the dielectric material, and a separate cobalt-containing capping layer that protects the copper from galvanic corrosion. This segmentation allows each layer to perform its specific function without causing harmful interactions.
2Reliability
If copper is deposited to fill the trench to form copper interconnect structures, then electrical conductivity is achieved, but copper ions migrate to the dielectric material causing time dependent dielectric breakdown
Solution Approach 1:
The cobalt-containing capping layer serves as an intermediary barrier that prevents copper ions from migrating into the dielectric material while allowing the copper interconnect structure to maintain its electrical conductivity function.
Solution Approach 2:
The copper-containing metal is recessed below the plane of the dielectric layer before final planarization, and the cobalt capping layer is deposited in advance to prevent copper ion migration during subsequent processing steps.
3Manufacturing precision
If the ruthenium liner layer is planarized with the dielectric layer, then surface flatness is achieved, but copper corrosion occurs due to exposure of copper to the environment
Solution Approach 1:
The copper-containing metal is recessed below the plane of the dielectric layer before final planarization, and the cobalt capping layer is deposited in advance to protect the copper from corrosion during subsequent processing and operation.
Solution Approach 2:
The cobalt-containing capping layer is deposited over the copper-containing metal before final planarization to provide protective cushioning against corrosion and oxidation, ensuring copper corrosion resistance while achieving the required surface flatness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach inhibits copper ion migration and TDDB, ensuring improved copper interconnect performance and dielectric integrity by avoiding copper corrosion and contamination.
Implementation Method 1
The liner/barrier layers are provided to prevent diffusion of conductive material into the dielectric material layer
Implementation Method 2
The liner/barrier layers are provided to prevent diffusion of conductive material into the dielectric material layer and to enhance adhesion of the conductive material to the walls of the trench
Implementation Method 3
The copper is encapsulated by depositing a capping layer over the copper
Implementation Method 4
The layers are then planarized to at least the plane
Data Source
AI summary
Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a dielectric layer defining a plane. In the method, the dielectric layer is etched to form trenches. Then, a ruthenium-containing liner layer is deposited overlying the dielectric layer. The trenches are filled with copper-containing metal. The method includes recessing the copper-containing metal in each trench to form a space between the copper-containing metal and the plane. The space is filled with a capping layer. The layers are then planarized to at least the plane.