Ruthenium Electrode Adhesion in Semiconductor Contact Holes

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Solution Overview

Problem

In semiconductor device fabrication, the use of ruthenium electrodes leads to increased contact resistance and regional lifting due to oxidation of the TiN diffusion barrier layer and poor adhesion with the etch stop layer, resulting in leaning of storage nodes.

Innovation Solution

A semiconductor device structure is developed with a titanium nitride diffusion barrier layer acting as an etch stop layer, and a ruthenium plug formed using physical vapor deposition (PVD) to reduce oxidation and enhance adhesion, preventing leaning of storage nodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If ruthenium electrode is formed using CVD or ALD method with oxygen reaction gas, then ruthenium electrode can be deposited, but contact resistance increases due to oxidation of TiN diffusion barrier layer

Engineering Contradiction:
Improveruthenium electrode depositionVSAvoidcontact resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A protective layer is formed on the TiN diffusion barrier layer before ruthenium electrode deposition to prevent oxidation. This preliminary protective action ensures that the TiN layer remains intact during the CVD or ALD process with oxygen reaction gas, thereby maintaining low contact resistance while enabling successful ruthenium electrode formation.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If ruthenium electrode is deposited, then electrode material is secured, but regional lifting occurs due to deteriorated adhesion with etch stop layer

Engineering Contradiction:
Improveelectrode material availabilityVSAvoidadhesion strength
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

An intermediate protective layer is introduced between the TiN diffusion barrier layer and the ruthenium electrode. This intermediate layer serves as a mediator that prevents direct contact between ruthenium and the etch stop layer, thereby preventing adhesion deterioration and regional lifting while still allowing the ruthenium electrode to be successfully deposited.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If full dip-out process is performed to form capacitor, then capacitor structure is created, but bottom oxide layer is wet etched causing storage node leaning

Engineering Contradiction:
Improvecapacitor structure formationVSAvoidstorage node alignment
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The protective layer is formed in advance on the TiN diffusion barrier layer before the full dip-out process. This preliminary protection prevents the bottom oxide layer from being wet etched during capacitor formation, thereby preventing storage node leaning while still allowing the capacitor structure to be successfully created.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces oxidation of the diffusion barrier layer and improves adhesion, preventing leaning and increasing the reliability of semiconductor devices by maintaining sufficient structural and electrical properties, especially in highly integrated memory devices with design rules of 45 nm or less.

Implementation Method 1

a ruthenium plug formed using physical vapor deposition (PVD)

Methodology Applied
Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Data Source

PatentUS7781336B2Semiconductor device including ruthenium electrode and method for fabricating the same
Publication Date: 2010.08.24 SK HYNIX INC
  • US7781336B2 patent drawing
  • US7781336B2 patent drawing
  • US7781336B2 patent drawing

AI summary

A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole, a diffusion barrier layer formed above the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole, a second plug formed on the diffusion barrier layer and filled in the contact hole, and a storage node coupled to and formed on the second plug.