Ruthenium Gate Stack Resistivity and Oxidation Control
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Solution Overview
Problem
Conventional MOS transistor gate structures using tungsten nitride and tungsten via layers face increased resistivity issues with reduced film thickness, making them less suitable for future node DRAM bitline applications and sensitive to oxidation.
Innovation Solution
A method involving the deposition of a ruthenium layer using a plasma sputter chamber with a high current electrostatic chuck at elevated temperatures, followed by annealing, to form a gate stack with a polysilicon layer, silicide layer, barrier layer, and a ruthenium layer, which results in lower resistivity films and minimizes ruthenium nitride formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tungsten is used to deposit barrier and via layers, then the structure provides good mechanical strength and barrier properties, but the resistivity increases with reduced film thickness
Solution Approach 1:
The patent changes the material parameter from tungsten to ruthenium, which inherently provides lower resistivity at reduced thicknesses while maintaining barrier properties. This material substitution directly addresses the resistivity increase problem in scaled-down tungsten structures.
Solution Approach 2:
The patent creates a composite structure with multiple layers including ruthenium barrier layer, ruthenium via layer, and ruthenium nitride spacer layer. This composite approach optimizes both mechanical strength and electrical conductivity by combining materials with complementary properties.
2Reliability
If tungsten nitride barrier layer is deposited using sputtering, then the barrier provides good adhesion and protection, but the structure becomes sensitive to oxidation
Solution Approach 1:
The patent changes the material composition from tungsten nitride to ruthenium-based layers, which exhibit superior oxidation resistance while maintaining adhesion properties. The ruthenium and ruthenium nitride combination provides both protective barrier function and oxidation stability.
3Productivity
If film thickness is reduced to enable miniaturization, then the device density increases, but the resistivity of tungsten films increases
Solution Approach 1:
The patent substitutes ruthenium for tungsten in the via and barrier layers. Ruthenium maintains low resistivity even at reduced thicknesses, enabling continued miniaturization without the resistivity penalty that plagues scaled-down tungsten structures.
4Reliability
If ruthenium layer is deposited and then nitride spacer is formed, then the spacer provides structural support, but ruthenium nitride formation increases resistivity
Solution Approach 1:
The patent segments the nitride formation process to occur only in the spacer region rather than throughout the entire ruthenium structure. This selective nitridation provides structural support where needed while preserving the low-resistivity ruthenium metal in the conductive via and barrier regions.
Solution Approach 2:
The patent applies different properties to different regions: the spacer region receives nitride treatment for structural support, while the via and barrier regions maintain pure ruthenium or ruthenium oxide for optimal electrical conductivity. This local differentiation resolves the conflict between structural needs and electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in lower resistivity films comparable to tungsten films, reducing sensitivity to oxidation and improving the effectiveness of gate stacks for future node DRAM bitline applications.
Implementation Method 1
physical vapor deposited (PVD) ruthenium
Implementation Method 2
Krypton is flowed into the chamber and excited into a plasma to deposit a ruthenium layer on the substrate
Implementation Method 3
the ruthenium layer on the substrate is annealed at a temperature greater than or equal to about 500° C
Implementation Method 4
The pedestal comprises a high current electrostatic chuck at a temperature greater than or equal to about 350° C
Data Source
AI summary
Ruthenium containing gate stacks and methods of forming ruthenium containing gate stacks are described. The ruthenium containing gate stack comprises a polysilicon layer on a substrate; a silicide layer on the polysilicon layer; a barrier layer on the silicide layer; a ruthenium layer on the barrier layer; and a spacer layer comprising a nitride on sides of the ruthenium layer, wherein the ruthenium layer comprises substantially no ruthenium nitride after formation of the spacer layer. Forming the ruthenium layer comprises sputtering the ruthenium in a krypton environment on a high current electrostatic chuck comprising a high resistivity ceramic material. The sputtered ruthenium layer is annealed at a temperature greater than or equal to about 500° C.