Ruthenium Interconnect Structure for Low-Resistance Fine Lines
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Solution Overview
Problem
Reducing the dimensions of interconnect structures in integrated circuit devices leads to increased resistance and deterioration of electrical characteristics due to material limitations.
Innovation Solution
An interconnect structure utilizing a ruthenium film with controlled crystal grain orientation and grain boundaries, embedded in a non-single crystalline material, to maintain electrical integrity at reduced dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimensions of interconnect structures are reduced, then the integration density and performance of integrated circuit devices are improved, but the resistance increases and electrical characteristics deteriorate
Solution Approach 1:
The patent applies parameter changes by controlling the crystal grain size (50-200 nm) and crystal orientation (c-axis perpendicular to substrate) of the ruthenium film. These parameter optimizations enable the material to maintain low resistance and good electrical characteristics even at reduced interconnect dimensions, resolving the contradiction between integration density improvement and electrical characteristic deterioration
Solution Approach 2:
The patent uses a composite structure consisting of a ruthenium film with specific crystalline properties embedded in a non-single crystalline material matrix. This composite approach allows the ruthenium film to provide excellent electrical conductivity while the surrounding non-single crystalline material provides structural support, thereby maintaining reliability at smaller dimensions
2Length of moving object
If the dimensions of interconnect structures are reduced, then the circuit device integration is improved, but the resistance increases due to material limitations
Solution Approach 1:
The patent optimizes the crystal grain size parameter to 50-200 nm and controls the crystal orientation with c-axis perpendicular to the substrate. These parameter changes reduce electron scattering at grain boundaries and maintain low resistance even when the interconnect dimension is reduced to fine line widths below 20 nm
Solution Approach 2:
The patent creates local quality differences by having the ruthenium film with specific crystalline properties (oriented c-axis, controlled grain size) embedded in a non-single crystalline material. This localized optimization of crystal structure in the ruthenium film regions provides excellent electrical conductivity where needed, while maintaining overall structural integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ruthenium film with controlled crystal grain orientation and grain boundaries effectively reduces electron scattering and resistance, maintaining electrical performance even at fine line widths below 20 nm.
Implementation Method 1
The ruthenium film with controlled crystal grain orientation and grain boundaries effectively reduces electron scattering and resistance
Implementation Method 2
post-annealing (or referred to as annealing) the ruthenium deposited product to form a ruthenium film
Implementation Method 3
a ruthenium film positioned on the film and including crystal grains
Data Source
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AI summary
An interconnect structure including a film including non-single crystalline material, and a ruthenium film positioned on the film and including crystal grains, wherein the crystal grains with <001> orientation of the ruthenium film has a crystal grain texturing factor, F001, of about 0.7 to 1, and an average crystal grain size of the ruthenium film is about 50 nm to about 200 nm.