Ruthenium Recessed Interconnect Layout for Via Misalignment Margin
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Solution Overview
Problem
As BEOL pitch scaling reduces metal line width, increasing resistivity and amplifying the risk of misalignment-induced shorting and increased via resistance due to the proximity of metal lines and vias, existing Ru subtractive etching processes face challenges in maintaining accurate alignment and reducing line resistance.
Innovation Solution
The introduction of recesses at the bottom surface of metal lines in the BEOL structure, ensuring direct contact with vias while avoiding contact with the dielectric layer, which increases the distance between metal lines and vias, thereby reducing the risk of shorting and improving via resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If metal line pitch is reduced to decrease line resistance, then line resistance decreases, but misalignment risk between metal lines and vias increases
Solution Approach 1:
The metal line structure is segmented into multiple sections: a first section that contacts the via, a second section separated by a recess, and a third section. This segmentation allows the first section to ensure reliable via contact while the recess provides alignment margin, resolving the contradiction between maintaining low resistance and tolerating misalignment.
Solution Approach 2:
The invention introduces a vertical dimension by creating recesses at the bottom surface of metal lines. This dimensional change allows the metal line to contact the via at a lower elevation while maintaining horizontal separation, thereby reducing misalignment risk without increasing line resistance.
2Quantity of substance
If metal line width is reduced to increase circuit density, then circuit density increases, but resistivity of metal line increases
Solution Approach 1:
The metal line structure employs local quality variation through recesses: areas over vias have direct contact for low resistance, while areas over dielectric have recesses for alignment margin. This localized structural differentiation allows narrow pitch while maintaining low overall resistance by concentrating conductive paths where needed.
3Quantity of substance
If distance between metal line and via is reduced to increase circuit density, then circuit density increases, but risk of contact shorting increases
Solution Approach 1:
By introducing vertical recesses, the invention creates a three-dimensional contact structure where metal lines can be positioned closer horizontally to increase density, while the vertical separation through recesses prevents shorting to the dielectric layer, thus resolving the contradiction between density and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the margin for metal misalignment, reduces contact shorting, and lowers via resistance by creating a larger distance between metal lines and vias, thereby improving the overall performance of the BEOL semiconductor structure.
Implementation Method 1
The adhesion layer may be removed by a wet recess process
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
A semiconductor device includes a dielectric layer, a plurality of vias formed in the dielectric layer, an adhesion layer deposited on a top surface of the dielectric layer, and a plurality of metal lines. A first metal line of the plurality of metal lines includes a first recess formed at a bottom surface of the first metal line such that a first section of the first metal line directly contacts the first via and a second section of the first metal line defined by the first recess does not directly contact the first via or the dielectric layer in which the first via is formed.