Ruthenium Seed Layer for Void-Free Copper ULSI Interconnects
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Solution Overview
Problem
Existing methods for forming copper seed layers for ULSI micro-interconnects face challenges such as insufficient adhesion, non-uniform plating, high impurity levels, and the need for multiple layers, which hinder the formation of uniform and void-free interconnects with low organic impurities.
Innovation Solution
A ruthenium electroplating layer is formed on a barrier layer, serving as a seed layer for copper electroplating, which ensures uniform thickness, low impurity levels, and eliminates the need for additional catalyst layers, thereby enhancing barrier properties and achieving uniform coverage on inner sidewalls and surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electroless copper plating is used to form a seed layer on a barrier layer, then copper deposition can be achieved, but the adhesion is insufficient and the plating is non-uniform
Solution Approach 1:
A ruthenium layer is introduced as an intermediate layer between the barrier layer and the copper electroplating layer. This ruthenium layer serves as a mediator that provides both adhesion to the barrier layer and a suitable surface for uniform copper electroplating, resolving the contradiction between adhesion and plating uniformity
Solution Approach 2:
The invention uses a composite structure consisting of multiple layers (barrier layer + ruthenium layer + copper electroplating layer) to achieve properties that individual layers cannot provide alone. The ruthenium layer combines adhesion properties with electroplating suitability, while the copper layer provides the conductive interconnect material
2Manufacturing precision
If a catalyst metal layer is formed before the barrier layer to enable uniform electroless plating, then plating uniformity improves, but the film thickness increases and impurity levels rise
Solution Approach 1:
The invention extracts and eliminates the catalyst metal layer from the structure by using copper electroplating instead of electroless plating. The ruthenium layer alone serves as the seed layer, removing the need for the additional catalyst layer and its associated impurities while maintaining plating uniformity
Solution Approach 2:
The ruthenium layer serves as a disposable seed layer that enables uniform electroplating but is not retained in the final structure. It performs its function of enabling uniform copper deposition and then serves as part of the barrier system, eliminating the need for permanent catalyst layer inclusion
3Quantity of substance
If CVD or ALD is used to form films with low impurity levels, then film purity improves, but organic impurities exceed 100 wt ppm and resistance increases
Solution Approach 1:
The invention replaces chemical vapor deposition (CVD) and atomic layer deposition (ALD) processes with physical vapor deposition (PVD) sputtering for forming the barrier and ruthenium layers. This substitution eliminates organic impurities introduced by chemical processes while maintaining excellent film quality and low electrical resistance
Solution Approach 2:
The invention changes the deposition method parameter from chemical processes (CVD/ALD) to physical processes (sputtering). This parameter change fundamentally alters the impurity profile by eliminating carbon-containing organic impurities while maintaining controlled film properties through physical deposition mechanisms
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ruthenium layer provides a uniform and impurity-free seed layer for copper electroplating, ensuring void-free micro-interconnects with improved barrier properties and reduced film thickness, addressing the limitations of existing methods.
Implementation Method 1
a ruthenium layer that has been formed by an electroplating process
Data Source
AI summary
A ULSI micro-interconnect member having a substrate and a ULSI micro-interconnect formed on the substrate, wherein the ULSI micro-interconnect includes a barrier layer formed on the substrate and a ruthenium electroplating layer formed on the barrier layer; the ULSI micro-interconnect member further including a copper electroplating layer formed using the ruthenium electroplating layer as a seed layer; and a process for fabricating the ULSI micro-interconnect members.