Ruthenium Via Plugs With Metal Cap Layers Against Cu Diffusion

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Solution Overview

Problem

The challenge in semiconductor device manufacturing is the occurrence of metal intermixing and void formation due to diffusion between copper (Cu) and ruthenium (Ru) metal layers, which leads to electrical disconnects and increased resistance in devices, especially as device density increases and feature sizes decrease.

Innovation Solution

A method involving the use of a self-assembled monolayer (SAM) and a metal cap layer, such as niobium, deposited between the ruthenium metal plugs and copper-containing metallization layers to prevent intermixing, where the SAM is selectively deposited on dielectric layers and the metal cap layer is formed directly on the ruthenium plugs, acting as a conductive barrier.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If copper (Cu) metal is used in multilayer metallization schemes for advanced integrated circuits, then device performance can be improved, but metal diffusion occurs resulting in metal intermixing and formation of voids in the metallization structure

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidmetal intermixing and void formation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A metal cap layer (such as ruthenium, rhodium, or iridium) is deposited between the copper metallization layer and the low-resistivity metal plug to act as a diffusion barrier. This intermediary layer prevents direct contact between copper and low-resistivity metals, thereby blocking metal diffusion and preventing intermixing and void formation while maintaining electrical connectivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The metallization structure employs a composite material system consisting of multiple layers: copper metallization layer, metal cap layer (diffusion barrier), and low-resistivity metal plug. This composite structure combines the advantages of copper (low cost, good conductivity) with low-resistivity metals (superior electrical performance) while using the metal cap layer to prevent harmful interactions between the materials.

Inventive Principle:
Principle #40Composite materials

2Productivity

If device density is increased to improve performance, then device area decreases, but via dimensions must be reduced leading to larger aspect ratios and increased risk of metal diffusion

Engineering Contradiction:
Improvedevice densityVSAvoidvia dimension control and metal diffusion prevention
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The metal cap layer serves as a critical intermediary component in high-density via structures with large aspect ratios. It provides a diffusion barrier throughout the via depth, preventing metal intermixing even when via dimensions are reduced and aspect ratios increased to achieve higher device density.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The via structure is segmented into distinct functional layers: the copper metallization layer at the bottom, the metal cap layer in the middle as a diffusion barrier, and the low-resistivity metal plug at the top. This segmentation allows each layer to perform its specific function while preventing harmful interactions, enabling reliable operation in high-density configurations.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces metal intermixing and void formation, ensuring reliable electrical connections and maintaining low resistance in multilevel metallization interconnects, thereby enhancing the performance and reliability of semiconductor devices.

Implementation Method 1

selectively depositing a first self-assembled monolayer (SAM) on the first dielectric layer

Methodology Applied
Scientific EffectSelf-assembly: Self-Assembly

Implementation Method 2

selectively depositing a first metal cap layer directly on the first ruthenium metal plug

Methodology Applied
Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Data Source

PatentUS20240363410A1Methods for making semiconductor devices that include metal cap layers
Publication Date: 2024.10.31 TOKYO ELECTRON LTD
  • US20240363410A1 patent drawing
  • US20240363410A1 patent drawing
  • US20240363410A1 patent drawing

AI summary

A method for forming a semiconductor device can include providing a substrate including a via in a dielectric layer, forming a ruthenium metal plug in the via, and at least part of the ruthenium metal plug can be formed directly on the dielectric layer in the via, forming a metal cap layer directly on the ruthenium metal plug, and forming a metallization layer, such as a copper-containing trench, over the ruthenium metal plug, such that the metal cap layer is between the metallization layer and the ruthenium metal plug, which can prevent intermixing of the ruthenium of the ruthenium metal plug with the metal or metals in the metallization layer.