Reader-Writer Lock Using CMPccXADD for High-Core Contention
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Solution Overview
Problem
Existing reader-writer locks in parallel and distributed computing systems face performance bottlenecks due to frequent contention and inefficient counter updates, particularly in high-core systems, leading to reduced scalability and increased CPU cycle costs.
Innovation Solution
The use of the CMPccXADD instruction for atomic comparison and manipulation of lock data structures, allowing for efficient check and update of read/write counters in a single operation, thereby reducing contention and improving scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional CAS (Compare-And-Swap) or NO-CAS methods are used for reader-writer lock operations, then the lock mechanism can function correctly, but CPU cycle costs increase and scalability deteriorates in high-core systems
Solution Approach 1:
The patent combines the comparison and addition operations into a single atomic instruction (CMPccXADD). Instead of performing separate compare-and-swap operations for each counter update, the invention merges these operations into one unified atomic operation that compares the lock data structure against a threshold and conditionally adds to counters simultaneously, reducing the number of CPU cycles required.
Solution Approach 2:
The patent introduces a threshold parameter in the lock data structure that enables conditional operations. By comparing the current lock state against this threshold and performing conditional additions based on the comparison result, the system optimizes counter updates by only performing necessary operations, thereby reducing unnecessary CPU cycles and improving overall lock operation efficiency.
2Reliability
If frequent counter updates are performed in reader-writer locks, then the lock state can be maintained accurately, but contention increases and performance bottlenecks occur
Solution Approach 1:
The patent merges multiple counter update operations into a single atomic CMPccXADD instruction. Instead of performing separate compare-and-swap operations for each counter modification, the invention combines these operations into one unified atomic operation that updates multiple counters simultaneously, reducing the frequency of atomic operations and thereby reducing contention while maintaining lock state accuracy.
Solution Approach 2:
The patent performs a preliminary comparison of the lock data structure against a threshold before performing counter updates. This preliminary action allows the system to determine whether updates are necessary before executing them, reducing unnecessary counter update operations and thereby reducing contention while ensuring that required updates are performed accurately.
3Reliability
If multiple threads contend for reader-writer lock simultaneously, then the lock provides proper synchronization, but scalability is reduced in high-core systems
Solution Approach 1:
The patent merges multiple synchronization operations into a single atomic CMPccXADD instruction that can handle multiple threads simultaneously. By combining counter comparisons and updates into one atomic operation, the system reduces the number of contention points and allows better parallelization across multiple cores, thereby improving scalability while maintaining synchronization correctness.
Solution Approach 2:
The patent uses threshold-based conditional operations to optimize contention handling. By comparing lock state against thresholds and performing conditional updates, the system reduces unnecessary atomic operations that cause contention, allowing multiple threads to proceed more efficiently while maintaining proper synchronization semantics.
Data Source
AI summary
Some aspects of the present disclosure relate to a non-transitory computer-readable medium storing instructions that, when executed by one or more processor circuitries, cause the one or more processor circuitries to perform a method for a computer system, comprising attempting to obtain a read or write lock for accessing a variable, by performing a write to a lock data structure based on a comparison between the lock data structure and at least one pre-defined condition, wherein the comparison and the write are performed together using a single instruction offered by an instruction set architecture of a processor circuitry of the computer system, and performing a read or write access to the variable if the read or write lock is successfully obtained.