Read-With-Invalidate Cache Line Command for Non-Volatile Memory Wear Reduction

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Solution Overview

Problem

In two-level memory systems, modified data in cache memory is often unnecessarily flushed to non-volatile memory, reducing the lifespan of far memory devices and increasing power consumption, as current techniques do not effectively differentiate between data needed for future operations and data that can be discarded after last access.

Innovation Solution

Implementing a read-with-invalidate (RWI) command to invalidate portions of cache lines with modified data upon last access, preventing these data from being copied to non-volatile memory when they are no longer needed, thereby extending the lifespan of far memory devices and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If modified data in cache memory is flushed to non-volatile memory to ensure data retention, then data reliability is improved, but the lifespan of far memory devices deteriorates due to increased write operations

Engineering Contradiction:
Improvedata retentionVSAvoidlifespan of far memory
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent introduces a new parameter state (invalidated) for cache lines that changes the flush behavior. When a cache line is marked as invalidated through the RWI command, the system parameter for that cache line changes from 'needs_flush' to 'can_discard', allowing the memory controller to differentiate between cache lines requiring persistence and those that can be discarded without flushing to far memory.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system implements feedback through the RWI command mechanism that provides information about data validity requirements. When software issues an RWI command, it provides feedback to the memory controller that the data can be discarded, enabling the controller to adjust its flush behavior dynamically based on actual data requirements rather than always flushing modified cache lines.

Inventive Principle:
Principle #23Feedback

2Reliability

If modified data is copied to non-volatile memory upon cache eviction, then data persistence is improved, but power consumption deteriorates due to unnecessary memory access operations

Engineering Contradiction:
Improvedata persistenceVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent changes the parameter state of cache lines by introducing an invalidation marker. When a cache line is invalidated via RWI command, its parameter changes from 'persistent' to 'discardable', which triggers different power management behavior in the memory controller, avoiding unnecessary activation of far memory interfaces and reducing power consumption.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent extracts the persistence requirement from the general cache eviction process. Instead of all modified cache lines being copied to far memory, the RWI command allows specific cache lines to be extracted from the flush queue, separating those that need persistence from those that can be discarded without power-consuming far memory access.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If all modified cache lines are flushed to far memory, then data integrity is improved, but system performance deteriorates due to increased far memory access operations

Engineering Contradiction:
Improvedata integrityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces a parameter change mechanism where cache lines can transition from a 'flush-required' state to a 'discardable' state through the RWI command. This parameter differentiation allows the memory controller to optimize flush operations, flushing only those cache lines that actually require persistence, thereby improving system performance by reducing unnecessary far memory access operations.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Instead of applying the flush operation to all modified cache lines (excessive action), the patent enables partial action by allowing selective invalidation through RWI commands. The memory controller performs flush operations only on cache lines that have not been invalidated, avoiding excessive far memory access operations and improving overall system performance.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10831658B2Read-with-invalidate modified data in a cache line in a cache memory
Publication Date: 2020.11.10 INTEL CORP
  • US10831658B2 patent drawing
  • US10831658B2 patent drawing
  • US10831658B2 patent drawing

AI summary

Provided are an apparatus and method to cache data in a first memory that is stored in a second memory. At least one read-with-invalidate command is received to read and invalidate at least one portion of a cache line having modified data. The cache line having modified data is invalidated in response to receipt of read-with-invalidate commands for less than all of the portions of the cache line.