RZ DAC Image Cancellation for Wideband Signal Conversion
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Solution Overview
Problem
Existing digital-to-analog converters (DACs) in wireless communication systems generate image signals due to sampling errors, which are challenging to filter out efficiently, especially in wideband applications, leading to power emissions at out-of-band frequencies and increased power consumption when trying to attenuate these signals.
Innovation Solution
The use of one or more return-to-zero (RZ) DACs in parallel with a zero-order hold DAC to cancel image signals, where RZ DACs generate analog outputs during specific portions of a clock cycle, and these outputs are combined to reduce the difference between the actual and ideal analog signals, thereby minimizing image signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional DAC is used for digital-to-analog conversion, then the conversion function is achieved, but image signals are generated due to sampling errors which are difficult to filter and cause power emissions at out-of-band frequencies
Solution Approach 1:
The patent segments the DAC function into multiple parallel DACs, each operating at a lower sampling rate (e.g., 1/2, 1/3, 1/4 of the original rate). Each segmented DAC generates fewer image signals, and their outputs are combined to achieve the overall high-resolution conversion while reducing total image signal power.
Solution Approach 2:
The patent introduces an intermediary combining network that merges the outputs of multiple parallel DACs. This combiner acts as a mediator to reconstruct the high-rate analog signal from multiple low-rate DAC outputs, effectively canceling image signals through proper phase and amplitude alignment.
2Object-generated harmful factors
If filtering is applied to attenuate image signals from a conventional DAC, then power emissions are reduced, but power consumption increases and filtering becomes inefficient especially in wideband applications
Solution Approach 1:
The patent applies preliminary action by reducing image signal generation at the source through parallel DAC architecture before the signal enters the filtering stage. By distributing the conversion function across multiple DACs operating at lower rates, image signals are inherently minimized, reducing the burden on subsequent filters and lowering overall power consumption.
3Measurement precision
If the sampling rate of a DAC is increased to improve conversion accuracy, then precision is improved, but image signals become more difficult to filter and power emissions increase
Solution Approach 1:
The patent segments the high-rate conversion function into multiple parallel low-rate DACs. Each DAC operates at a manageable sampling rate, generating fewer image signals that are easier to filter. The combination of these segmented outputs achieves the equivalent of high-rate conversion without the associated filtering complexity.
Data Source
AI summary
Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example device for digital-to-analog conversion generally includes: a digital-to-analog converter (DAC) having an input coupled to an input node of the device; a first return-to-zero (RZ) DAC having an input coupled to an input node of the device; and a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the first RZ DAC is coupled to a second input of the combiner.