SAADC Capacitor Array Sorting for Improved Conversion Linearity
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Solution Overview
Problem
Existing SAADC circuits face non-ideal linearity due to capacitor mismatches caused by manufacturing processes and environmental changes, which become more pronounced with higher resolution requirements.
Innovation Solution
A SAADC circuit with a control circuit that sorts unit capacitors based on their capacitances to configure higher-bit capacitors within a predetermined linearity range, using a capacitor enabling circuit to selectively couple capacitors to reference voltages through a successive approximation mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If capacitor array is used in SAADC circuit, then conversion function is achieved, but linearity becomes non-ideal due to capacitor mismatches
Solution Approach 1:
The patent applies preliminary action by performing a sorting process on unit capacitors during an initializing mode before the actual conversion operation. The control circuit measures the capacitance values of all unit capacitors and arranges them in ascending order, then configures the higher-bit capacitors based on this pre-sorted arrangement to ensure optimal linearity. This preliminary sorting action eliminates the need for manual calibration and ensures accurate conversion without requiring extremely tight manufacturing tolerances.
2Measurement precision
If higher resolution is required, then conversion precision is improved, but accuracy of capacitor ratios becomes more critical and difficult to achieve
Solution Approach 1:
For higher resolution conversions, the patent enhances the preliminary action by performing multiple sorting stages. After the initial sorting, the control circuit further sorts and reconfigures the unit capacitors to ensure that the ratios among the capacitances of higher-bit capacitors meet the stringent requirements for high-resolution conversion. This multi-stage preliminary sorting enables the circuit to achieve high resolution without requiring extremely tight manufacturing tolerances.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the configuration parameters of the capacitor array based on the measured capacitance values. The control circuit modifies which unit capacitors are grouped together to form higher-bit capacitors, changing the effective capacitance ratios to achieve the desired linearity and resolution performance.
3Measurement precision
If unit capacitors are sorted and configured to optimize linearity, then linearity parameter is improved, but additional control operations are required
Solution Approach 1:
The patent applies self-service by implementing an automated sorting and configuration process that eliminates the need for external manual calibration. The control circuit autonomously measures the capacitance values of all unit capacitors, sorts them according to their actual values, and configures the higher-bit capacitors to achieve optimal linearity. This self-service approach simplifies the overall system by removing the need for external calibration equipment or manual adjustment procedures.
Solution Approach 2:
The patent performs all necessary sorting and configuration operations during an initializing mode before the actual conversion operation begins. This preliminary action consolidates the control complexity into a one-time setup phase, allowing the conversion operation itself to proceed with simple, repetitive steps. The linearity optimization is achieved beforehand, so no complex control operations are needed during the actual conversion process.
4Measurement precision
If capacitor mismatches occur due to manufacturing or temperature changes, then linearity deteriorates, but reconfiguration is needed to maintain accuracy
Solution Approach 1:
The patent performs the sorting and configuration operation during an initializing mode that can be executed before deployment or at the beginning of operation. By measuring the actual capacitance values and arranging the capacitors in the optimal configuration beforehand, the system compensates for manufacturing variations and initial temperature effects. This preliminary action ensures that the capacitor array starts with optimal linearity, and the configuration can be re-executed if temperature drift occurs during operation.
Data Source
AI summary
The present invention discloses a SAADC circuit having optimized linearity. A lower-bit capacitor array includes lower-bit capacitors. A higher-bit capacitor array includes unit capacitors. In an initializing mode, a control circuit sorts the unit capacitors according to unit capacitances thereof such that the unit capacitors are configured to be higher-bit capacitors having a linearity parameter within a predetermined range. In an operation mode, the capacitor array receives an analog input signal and a reference voltage to generate an analog output signal, a comparator generates a comparison result according to the analog output signal and the control circuit generates an enabling signal according to the comparison result based on the successive approximation mechanism to selectively enable the higher-bit and the lower-bit capacitors to connect to the reference voltage by using the capacitor enabling circuit and outputs a digital output signal according to the final comparison result.