Parallel Saber Multiplier for Non-Prime Modulo Hardware
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Solution Overview
Problem
The Saber algorithm's efficiency in modulo multiplication is hindered by excessive operation expenditure, leading to high computation complexity and low computation speed, particularly due to constraints on modulus being a prime number and increased circuit area expenditure.
Innovation Solution
A parallel multiplier for the Saber algorithm comprising a coefficient memory, two parallel pre-adding circuits, three parallel multiplication circuits, and a post-adding circuit, employing a divide-and-conquer strategy to perform parallel computations, allowing modulo operations with non-prime numbers and reducing circuit area expenditure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the Karatsuba algorithm is used for modulo multiplication in the Saber algorithm, then computation complexity is reduced, but the modulus must be a prime number which constrains the scheme
Solution Approach 1:
The polynomial multiplication is divided into multiple segments using a divide-and-conquer strategy. The polynomials are split into high and low degree parts, and multiplication is performed on these segments in parallel, avoiding the need for prime modulus while reducing computation complexity.
Solution Approach 2:
The invention transitions from sequential scalar multiplication to parallel polynomial coefficient multiplication by organizing computations in a multi-dimensional array structure, allowing simultaneous computation of multiple coefficient products without requiring prime modulus constraints.
2Productivity
If multiple layers of Karatsuba algorithm are called to improve computation efficiency, then computation speed increases, but extra circuit area expenditure is caused
Solution Approach 1:
The computation is segmented into three parallel multiplication circuits that operate simultaneously on different polynomial coefficient combinations, eliminating the need for repeated sequential Karatsuba calls and reducing circuit area while maintaining efficiency.
Solution Approach 2:
Multiple multiplication operations are merged into a single parallel execution stage using three multiplication circuits, combining what would otherwise require multiple sequential Karatsuba algorithm calls into one simultaneous operation, reducing both time and area.
3Area of stationary object
If traditional sequential multiplication is used, then circuit area is small, but computation speed is low
Solution Approach 1:
The polynomial multiplication is segmented into three independent parallel computation paths that can be executed simultaneously, increasing computation speed while keeping each individual circuit path relatively compact.
Solution Approach 2:
The parallel architecture enables continuous computation of multiple coefficient products simultaneously rather than sequentially, maintaining high utilization of computational resources throughout the multiplication process.
Data Source
AI summary
A parallel multiplier for the Saber algorithm comprises a coefficient memory, two parallel pre-adding circuits, three parallel multiplication circuits and a post-adding circuit. The coefficient memory, the two parallel pre-adding circuits, the three parallel multiplication circuits and the post-adding circuit adopt a divide-and-conquer strategy, the two parallel pre-adding circuits perform parallel computation, and the three parallel multiplication circuits perform parallel computation, such that the computation time of modulo multiplication is shorted; the modulo operation of non-prime numbers is realized by limiting the bit width, such that the constraint that the modulus is a prime number is avoided; and the Karatsuba algorithm is called once, such that extra circuit area expenditure is reduced. Thus, the parallel multiplier for the Saber algorithm is implemented by hardware, low in computation complexity, not limited by the constraint that the modulus is a prime number, and low in circuit area expenditure.