Saboteur Circuit Insertion for FPGA Fault Mitigation
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Solution Overview
Problem
Critical systems face challenges in maintaining operation in the presence of hardware faults, such as those caused by particle strikes, radiation, manufacturing defects, or maliciously injected logic, which can lead to vulnerabilities and failures.
Innovation Solution
A method for circuit modification that involves obtaining a netlist, inserting saboteur circuits to simulate faults, configuring an FPGA to implement the circuit and saboteur circuits, activating the saboteur circuits to detect faults, and modifying the circuit by inserting redundant logic elements to mitigate faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If saboteur circuits are inserted to detect faults, then fault detection capability is improved, but circuit complexity increases
Solution Approach 1:
The patent introduces saboteur circuits as intermediary elements that are inserted into the target circuit to simulate faults. These saboteur circuits act as mediators between the test environment and the circuit under test, enabling fault detection without requiring direct modification of the circuit's core functionality. The saboteur circuits can be selectively activated and deactivated, allowing comprehensive fault testing while maintaining the original circuit's operational integrity.
Solution Approach 2:
The patent segments the fault detection process by dividing it into multiple test iterations, where different saboteur circuits are activated in sequence. Instead of having all saboteur circuits active simultaneously, the system tests one or a few at a time, reducing the complexity burden at any given moment while still achieving comprehensive fault coverage across all possible fault scenarios.
2Reliability
If redundant logic elements are inserted to mitigate faults, then system reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by inserting redundant logic elements and majority voter circuits before faults actually occur in the critical system. The redundancy is pre-configured based on fault detection results from saboteur circuit testing, so that when real faults occur, the system already has the necessary backup mechanisms in place to maintain operation. This proactive approach improves reliability without requiring complex real-time decision-making during fault events.
Solution Approach 2:
The patent applies local quality by selectively adding redundancy only to specific nets or circuit portions that are identified as vulnerable through saboteur circuit testing. Instead of uniformly adding redundancy throughout the entire system, the method targets only those critical paths that demonstrate susceptibility to faults, thereby improving overall system reliability while minimizing the increase in device complexity to only where it is most needed.
3Reliability
If multiple saboteur circuits are tested sequentially, then fault coverage is improved, but testing time increases
Solution Approach 1:
The patent applies partial action by testing one or a few saboteur circuits at a time rather than activating all saboteur circuits simultaneously or testing every possible combination. This selective approach achieves sufficient fault coverage for critical faults without the exponential time cost of exhaustive testing. The method tests enough saboteur circuits to identify vulnerable paths and justify redundancy insertion, without requiring complete enumeration of all possible fault scenarios.
Data Source
AI summary
A method for circuit modification for fault mitigation including: obtaining a netlist defining a circuit; inserting at least one saboteur circuit into a first net of the netlist; configuring an FPGA to implement the first net and the at least one saboteur circuit; activating a first of the at least one saboteur circuits; determining whether the first net experiences a fault; and upon determining that the first net experiences a fault, modifying the first net by inserting at least one redundant circuit into the first net.