Self-Aligned Contact Structure with Isolated Silicon Nitride Film
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Solution Overview
Problem
The miniaturization of semiconductor integrated circuit devices faces challenges due to variations in alignment during the photolithography process, leading to increased contact hole design sizes and difficulties in scaling down the self-aligned contact (SAC) structure, particularly in Dynamic Random Access Memory (DRAM) where the silicon nitride film affects gate threshold voltage and etching processes.
Innovation Solution
A semiconductor integrated circuit device and manufacturing method that isolates the silicon nitride film from the semiconductor substrate, using selective epitaxial growth to form a silicon layer on the diffusion layer and burying a silicon oxynitride or silicon oxide film in the gap between the gate electrode and the silicon layer, facilitating dry etching and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a silicon nitride film is used as an etching stopper in the self-aligned contact process, then the etching process is simplified and alignment margin is reduced, but the silicon nitride film causes gate threshold voltage variation due to hot carrier trapping
Solution Approach 1:
The device is segmented into two regions: a first region with the silicon nitride film serving as etching stopper, and a second region without the silicon nitride film where the gate electrode contacts the semiconductor substrate. This segmentation allows the etching process to benefit from the silicon nitride film while preventing hot carrier trapping in the transistor operation region.
Solution Approach 2:
The silicon nitride film is extracted or removed from the second region where the gate electrode is formed, so that the gate electrode can be in direct contact with the semiconductor substrate. This extraction eliminates the harmful effect of hot carrier trapping while preserving the etching stopper function in the first region.
2Manufacturing precision
If the contact hole design size is increased to account for alignment variation, then alignment robustness is improved, but device miniaturization is hindered
Solution Approach 1:
The self-aligned contact process uses the sidewall of the gate electrode itself as the alignment reference for forming the contact hole. This self-service mechanism eliminates the need for additional alignment margins, allowing contact holes to be miniaturized without compromising alignment robustness.
3Productivity
If the self-aligned contact structure is miniaturized for DRAM applications, then device density is improved, but the silicon nitride film continues to affect etching and threshold voltage
Solution Approach 1:
Different regions of the device are assigned different qualities: the first region has the silicon nitride film for etching stopper function, while the second region has direct gate-to-substrate contact for stable threshold voltage. This local differentiation allows miniaturization in DRAM while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach inhibits gate threshold voltage variation by isolating the silicon nitride film from the substrate, simplifies dry etching, and reduces parasitic capacitance, stabilizing memory reading operations and facilitating miniaturization of the SAC structure.
Implementation Method 1
a silicon layer formed on the exposed surface of the diffusion layer by selective epitaxial growth
Data Source
AI summary
A semiconductor integrated circuit device having a pair of adjacent MOS transistors and a contact plug 33, buried into a contact hole formed by a self-aligned contact process using a silicon nitride film as an etching stopper and electrically connected to diffusion layers 2 and 3 constituting the MOS transistor on a silicon substrate 21 surrounded by a device isolation region 4: wherein a silicon layer 28 is formed on the exposed surface of the diffusion layers 2 and 3 by selective epitaxial growth, which is in contact with an end of each gate insulation film 22 on the diffusion layer side; an insulation film 27′ composed of a silicon oxynitride film or a silicon oxide film is buried between the each gate electrode and the silicon layer 28 while being in contact with the gate insulation film 22; and the silicon nitride films 26, 29′, and 32 are isolated from the silicon substrate 21 by the insulation film 27′.