Self-Aligned Contact Layer Implantation for Etch-Resistant Fins
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the etching of backside self-aligned contact (SAC) layers during pre-silicide cleaning processes, which compromises the integrity of semiconductor fins and potentially leads to electrical shorts.
Innovation Solution
An implantation process is employed to modify the dielectric properties of the backside SAC layer, enhancing its etch resistance to protect the semiconductor fin during pre-silicide cleaning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the backside SAC layer is made thin to enable device scaling and space saving, then the device can be scaled down and space can be saved, but the SAC layer becomes susceptible to etching during pre-silicide cleaning process
Solution Approach 1:
The patent changes the physical-chemical parameters of the SAC layer by forming a gradient structure with varying composition (SiO2 to SiN ratio) and density from bottom to top. This parameter gradient provides etch resistance to the thin SAC layer during pre-silicide cleaning while maintaining the thin profile needed for device scaling.
Solution Approach 2:
The patent applies different material properties to different regions of the SAC layer. The lower portion has higher SiO2 content for adhesion and etch resistance, while the upper portion has higher SiN content for protection. This local quality differentiation enables the thin SAC layer to withstand etching processes.
2Reliability
If the SAC layer is made thicker to improve etch resistance, then the SAC layer can withstand pre-silicide cleaning better, but device scaling and space saving are compromised
Solution Approach 1:
Instead of increasing thickness, the patent changes the compositional parameters within the existing thin layer thickness. The gradient structure with varying SiO2/SiN ratio provides enhanced etch resistance without increasing the overall SAC layer thickness, thus maintaining device scaling benefits.
Solution Approach 2:
The patent creates a composite SAC layer structure combining SiO2 and SiN in a gradient configuration. This composite structure provides superior etch resistance compared to homogeneous materials of the same thickness, enabling thin SAC layers to withstand pre-silicide cleaning processes.
3Reliability
If an implantation process is added to enhance etch resistance, then the SAC layer can withstand pre-silicide cleaning, but the manufacturing process complexity increases
Solution Approach 1:
The patent performs the implantation process early in the manufacturing sequence, before patterning and other critical steps. This preliminary action enhances SAC layer etch resistance before subsequent processes, preventing the need for rework or additional protective measures later.
Solution Approach 2:
The patent combines the implantation process with existing manufacturing flow by integrating it into the SAC layer formation sequence. The implantation is performed immediately after SAC layer deposition and before patterning, merging multiple functions into a coordinated process sequence that minimizes overall complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced etch resistance of the SAC layer prevents etching during pre-silicide cleaning, ensuring the semiconductor fin's integrity and preventing electrical contact with the contact plug, thereby maintaining device reliability.
Implementation Method 1
An implantation process is introduced to modify the dielectric properties of the backside SAC layer
Data Source
AI summary
A semiconductor device includes a semiconductor fin, an epitaxial region located on a side of the semiconductor fin, a silicide layer disposed on the epitaxial region, a contact plug disposed on the silicide layer and over the epitaxial region, and a self-aligned contact (SAC) layer disposed on the semiconductor fin. At least a part of the SAC layer is implanted with at least one implantation element. The semiconductor fin is spaced apart from the contact plug by the SAC layer.