SAC Line Mask for Compact DRAM Sub-Word Drivers
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Solution Overview
Problem
The existing SAC hole technique for forming contact plugs in semiconductor memory devices results in a long distance between contact plugs and gate electrodes, leading to increased size and reduced density of sub-word line driving circuits, which is a challenge in miniaturizing DRAMs without degrading performance.
Innovation Solution
The use of a SAC line technique with line-shaped openings in a mask allows for efficient etching of contact holes, reducing the distance between contact plugs and gate electrodes, enabling a more compact layout of select-line driving circuits by allowing etchant to move efficiently within the holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the SAC hole technique is used to form contact plugs, then contact plugs can be formed in self-alignment, but the distance between contact plugs and gate electrodes becomes long
Solution Approach 1:
The mask layer is divided into multiple segments with different patterns: a first mask pattern for forming contact holes and a second mask pattern for forming gate electrodes. This segmentation allows independent optimization of each feature's formation process, enabling reduced contact hole dimensions while maintaining proper alignment with gate electrodes.
Solution Approach 2:
The invention transitions from a single mask layer approach to a multi-layer mask structure with different patterns formed at different stages. By using separate mask layers (first mask layer for contact holes, second mask layer for gate electrodes), the process achieves precise spatial control in multiple dimensions, reducing the distance between contact plugs and gate electrodes while maintaining self-alignment.
2Reliability
If a large gate width is used to secure sufficient current driving capacity, then transistor performance is improved, but the installation area of sub-word line driving circuits increases
Solution Approach 1:
The invention reorganizes the spatial arrangement of transistors by forming gate electrodes in a multi-dimensional layout rather than a simple linear arrangement. By using multiple mask patterns and layering techniques, gate electrodes can be positioned more efficiently in the lateral direction, reducing the overall installation area while maintaining sufficient gate width for current driving capacity.
Solution Approach 2:
The invention merges the formation processes of contact holes and gate electrodes into an integrated multi-step patterning sequence. By combining these operations and using shared process steps, the layout efficiency is improved, allowing transistors to be packed more densely while maintaining adequate gate dimensions for required current driving capacity.
3Reliability
If thick gate gap and sidewall are used to prevent gate electrode damage, then gate electrode protection is improved, but the distance between contact plug and gate electrode increases
Solution Approach 1:
The protective structure is segmented into distinct components: gate gap formed first, then sidewall formed subsequently. This segmentation allows precise control of each protective element's thickness and positioning. The gate gap can be optimized for initial protection during contact hole formation, while the sidewall provides additional protection during gate electrode formation, enabling reduced overall dimensions while maintaining adequate protection.
Solution Approach 2:
The gate gap is formed as a preliminary protective structure before contact holes are etched. This preliminary action provides gate electrode protection during the contact hole formation process. By establishing this protective layer first, the subsequent gate electrode can be formed closer to the contact plug without risking damage, as the gate gap already provides the necessary protection during the critical etching step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a reduction in the size of select-line driving circuits, specifically sub-word line drivers, without compromising performance, allowing for a more compact DRAM design and improved manufacturing efficiency.
Implementation Method 1
selectively removing the interlayer insulation layer by using the mask layer and the insulation film as a mask to form the contact holes
Data Source
AI summary
A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.