Sacrificial-Layer Bit Line Layout for High-Density Vertical Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration level of transistors in existing memory technologies restricts storage density, as reducing transistor size leads to performance decline due to the narrow and short channel effects, making it challenging to improve storage density without compromising transistor performance.
Innovation Solution
A semiconductor structure is formed by creating separate active pillars on a substrate with a gap between them, filled with a bit line, and topped with semiconductor pillars, which allows for improved storage density while maintaining transistor performance through a method involving sacrificial layers, etching, and conductive material filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the channel size of the transistor is reduced to improve storage density, then the storage density of the memory is improved, but the performance of the transistor declines due to narrow channel effect and short channel effect
Solution Approach 1:
The patent transitions from planar transistors to vertically standing transistors, changing the dimensional orientation of the channel from horizontal to vertical. This allows the channel to extend in the vertical direction rather than being constrained horizontally, enabling continued scaling in the planar direction without suffering from the same narrow and short channel effects that limit planar transistor performance.
Solution Approach 2:
The transistor channel is segmented into distinct vertical sections with different doping regions (first doped region, second doped region, third doped region) along its length. This segmentation allows for optimized electrical characteristics in different portions of the channel, improving overall transistor performance while maintaining the vertical architecture that enables higher storage density.
2Quantity of substance
If the size of the transistor is reduced to improve storage density, then the storage density of the memory is improved, but the further improvement of the size of the transistor is restricted by narrow channel effect and short channel effect
Solution Approach 1:
By standing the transistor channel vertically rather than keeping it planar, the invention opens up the vertical dimension for scaling. This allows continuous reduction of the transistor footprint in the planar direction without hitting the performance walls that constrain further size reduction in conventional planar devices.
Solution Approach 2:
Multiple vertically standing transistors are arranged in an array configuration, with each transistor containing nested doped regions within its channel structure. This nested arrangement of functional regions within the vertical channel enables complex functionality in a compact footprint, supporting further miniaturization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances storage density by reducing transistor size without compromising performance, addressing the limitations of existing technologies by forming a semiconductor structure with separate active pillars and bit lines that support improved memory cell integration.
Implementation Method 1
the active layer and the sacrificial layer are etched up to a surface of the substrate to form a plurality of active lines arranged in parallel
Implementation Method 2
the sacrificial layer is removed along the opening hole to form a gap between a bottom of the active lines and the substrate
Implementation Method 3
a conductive material is filled in the gap to form a bit line extending along the first direction
Data Source
AI summary
A method for forming a semiconductor structure includes: providing a substrate, a sacrificial layer and active layer on sacrificial layer being formed on the substrate; etching the active layer and sacrificial layer up to a surface of the substrate to form a plurality of active lines arranged in parallel and extending along first direction; filling an opening located between two adjacent ones of active lines to form a first isolating layer; etching an end of active lines to form an opening hole; removing sacrificial layer along opening hole, to form a gap between a bottom of the active lines and substrate; filling a conductive material in the gap to form a bit line extending along first direction; patterning the active lines to form a plurality of separate active pillars arrayed along first direction and second direction; and forming semiconductor pillars on top surfaces of respective ones of the active pillars.