Sacrificial Block Packaging for Logic Die Testing

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Solution Overview

Problem

Current 3D-integrated circuit packaging technologies face challenges in achieving high interconnect density and independent testing of logic dies without increasing manufacturing costs, particularly in achieving the required interconnect density for high bandwidth applications like Wide I/O DRAM and thermal coupling between dies.

Innovation Solution

The method involves embedding a sacrificial block with the logic die in a mold substrate, creating an opening by removing the block to expose contacts, allowing for independent testing and subsequent bonding of memory dies, and then overmolding to form a reconstructed wafer that can be singulated into separate packages, eliminating the need for TSV inserts and enabling high-density interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If TSV inserts are used to achieve high interconnect density, then interconnect density is improved, but manufacturing cost increases

Engineering Contradiction:
Improveinterconnect densityVSAvoidmanufacturing cost
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent removes the TSV insert component entirely from the packaging structure. Instead of using a separate TSV insert embedded in the mold substrate, the invention integrates the through-silicon via functionality directly into the logic die itself, eliminating the need for additional TSV inserts and reducing manufacturing complexity and cost while maintaining high interconnect density

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the TSV insert functionality with the logic die structure. The logic die is designed to include its own through-silicon vias that provide the necessary interconnects, combining what were previously separate components (logic die + TSV insert) into a single integrated unit, thereby simplifying the overall packaging structure

Inventive Principle:
Principle #5Merging (Combining)

2Ease of operation

If logic die is embedded in mold substrate with TSV insert, then independent testing is enabled, but device complexity increases

Engineering Contradiction:
Improveindependent testing capabilityVSAvoidpackaging structure complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent removes the TSV insert component from the packaging structure. The logic die is designed to include its own through-silicon vias that provide the necessary interconnects, combining what were previously separate components (logic die + TSV insert) into a single integrated unit, thereby simplifying the overall packaging structure

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The logic die serves multiple functions: it performs its primary computational role while also providing its own through-silicon via interconnects that would previously have been provided by a separate TSV insert. This multi-functionality eliminates the need for additional components and simplifies the packaging structure

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If through-package vias are used with limited pitch, then package construction is simplified, but interconnect density is insufficient for high bandwidth applications

Engineering Contradiction:
Improvepackage construction simplicityVSAvoidinterconnect density
Core Design Contradiction:
Ease of manufactureVSQuantity of substance

Solution Approach 1:

The patent changes the pitch parameter of the through-silicon vias by designing the logic die with TSVs at a much finer pitch (e.g., 50μm or less) compared to traditional through-package vias (several 100μm pitch). This parameter change enables high interconnect density required for high bandwidth applications while maintaining the simplicity of the packaging construction

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11367705B2Method for packaging semiconductor dies
Publication Date: 2022.06.21 INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
  • US11367705B2 patent drawing
  • US11367705B2 patent drawing
  • US11367705B2 patent drawing

AI summary

A method of using sacrificial structures in a mold substrate for packaging a first die and one or more second dies or stacks thereof is disclosed. The method allows testing of the first die prior to mounting the second dies, without requiring a TSV insert. In one aspect, a block of sacrificial material is embedded together with the first die in a first mold substrate and to one side of the first die. The removal of the block creates an opening. The method is configured so that contacts are exposed at the bottom of the opening, the contacts being electrically connected to corresponding contacts on the first die. This may be realized by bonding both the die and the sacrificial block to a redistribution layer, or by mounting a bridge device between the first die and the block prior to a first overmolding applied for producing the first mold substrate. A second die or a stack of second dies is mounted in the opening and bonded to the exposed contacts, after which a second mold substrate is produced, embedding the second die or dies.