Sacrificial Blocking Layers for Selective Oxidation in MOS Transistors
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Solution Overview
Problem
The miniaturization of MOS devices leads to the short channel effect, resulting in reduced gate controllability, hot carrier generation, and decreased reliability, while reoxidation processes to mitigate this issue can increase gate insulating layer thickness, compromising operating speed.
Innovation Solution
A method of manufacturing semiconductor integrated circuit devices involves creating distinct transistor regions with different gate insulating layers and spacer structures, allowing selective reoxidation in regions requiring improved reliability, while maintaining uniformity and preventing excessive thickness increases in other regions, thus optimizing performance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reoxidation process is performed to remove hot carrier effect, then reliability is improved, but gate insulating layer thickness increases due to bird's beak phenomenon, resulting in reduction of operating speed
Solution Approach 1:
The patent applies local quality by performing reoxidation selectively in specific transistor regions where reliability is prioritized, rather than uniformly across all transistors. This allows the gate insulating layer to be thickened locally in regions requiring hot carrier effect mitigation, while maintaining thinner layers in speed-critical regions, thus resolving the contradiction between reliability improvement and operating speed preservation
Solution Approach 2:
The semiconductor device is segmented into multiple transistor regions with different characteristics - some regions undergo reoxidation for reliability while others maintain original structure for speed. This segmentation allows different parts of the device to be optimized for different functions, enabling simultaneous achievement of high reliability in critical regions and high operating speed in performance-critical regions
2Reliability
If all transistors are subjected to reoxidation process to remove hot carrier effect, then reliability is improved, but characteristic requirements of some transistors requiring faster operating speed are deteriorated
Solution Approach 1:
Different transistor regions are assigned different local qualities through selective reoxidation - reliability-critical regions receive the reoxidation treatment while speed-critical regions maintain their original characteristics. This local differentiation allows each transistor type to be optimized for its specific function within the same integrated circuit
Solution Approach 2:
The device is divided into functionally distinct transistor regions that can be independently processed. This segmentation enables the circuit to contain both high-reliability transistors (subjected to reoxidation) and high-speed transistors (not subjected to reoxidation), providing adaptability to meet diverse functional requirements within a single device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables transistors to meet specific requirements by avoiding hot carrier effects and maintaining operating speed, enhancing the stability and performance of semiconductor integrated circuit devices by tailoring each transistor region's characteristics effectively.
Implementation Method 1
conformally forming a second oxide layer on lateral surfaces of the second gate insulating layer and the second gate and on an exposed surface of the semiconductor substrate by performing oxidation in the second transistor region
Data Source
AI summary
Provided are a more stable semiconductor integrated circuit device and a method of manufacturing the same. The method includes providing a semiconductor substrate comprising a first transistor region having a stacked structure of a first gate insulating layer and a first gate and a second transistor region having a stacked structure of a second gate insulating layer and a second gate, forming a blocking layer in the first transistor region, conformally forming a second oxide layer on lateral surfaces of the second gate insulating layer and the second gate and on an exposed surface of the semiconductor substrate by performing oxidation in the second transistor region, removing the blocking layer of the first transistor region, forming a pre-spacer layer on the entire surface of the semiconductor substrate, forming a first spacer by anisotropically etching the pre-spacer layer of the first transistor region and forming a second spacer by anisotropically etching the second oxide layer and the pre-spacer layer of the second transistor region, and forming source/drain regions in the semiconductor substrate to complete a first transistor and a second transistor.