Self-Aligned Sacrificial Capping for Trench Silicide

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Solution Overview

Problem

Current FinFET devices in the 14 nm technology node and beyond face challenges with contact resistance, particularly in scaling down where larger critical dimensions for trench silicide lead to gate shorts and increased doping concentration methods are not effectively implemented for both p-channel and n-channel field-effect transistors without additional masking layers.

Innovation Solution

The integration scheme involves forming a larger bottom critical dimension of trench silicide for n-channel FinFETs with a self-aligned trench implant for p-channel FinFETs, using a sacrificial epitaxial capping layer to increase surface area and prevent erosion, and filling silicide trenches with metal to reduce contact resistance without additional masking layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If larger critical dimensions are used for trench silicide to increase surface area, then contact resistance is reduced, but gate to trench silicide shorts and shorting between neighboring silicide trenches occur

Engineering Contradiction:
Improvecontact resistanceVSAvoidgate to trench silicide shorts
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A sacrificial epitaxial capping layer is formed over the trench silicide structure before final processing. This preliminary protective layer prevents erosion during etching and maintains the intended critical dimensions, allowing larger bottom CDs to be achieved without causing shorts to gates or neighboring trenches.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs selective epitaxial growth to create a capping layer with different material composition and properties than the underlying trench silicide. This parameter change enables the capping layer to protect the trench silicide during subsequent processing while allowing the trench silicide to maintain larger dimensions for reduced contact resistance.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If higher doping concentration is used in source/drain regions to reduce contact resistance, then contact resistance is improved, but implementation becomes difficult without additional masking layers

Engineering Contradiction:
Improvecontact resistanceVSAvoidmasking layers
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The sacrificial epitaxial capping layer serves multiple functions automatically: it protects the trench silicide during etching, defines the implantation regions through its presence, and can be selectively removed. This self-service approach eliminates the need for additional masking layers to achieve selective doping in PFET and NFET regions.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The sacrificial epitaxial capping layer performs multiple functions: it acts as a protective barrier during trench silicide formation, serves as a self-aligned mask for dopant implantation in one device type while exposing the other, and can be selectively removed. This multi-functionality reduces device complexity by eliminating separate masking steps.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Object-affected harmful factors

If narrow trenches are used to isolate neighboring trenches, then isolation is achieved, but titanium silicide surface area is sacrificed

Engineering Contradiction:
Improveisolation from neighboring trenchesVSAvoidtitanium silicide surface area
Core Design Contradiction:
Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The sacrificial epitaxial capping layer enables local differentiation of trench dimensions. The bottom critical dimension can be enlarged to increase titanium silicide surface area for reduced contact resistance, while the top critical dimension remains constrained by the capping layer thickness to maintain isolation from neighboring trenches. This local quality approach allows simultaneous optimization of both surface area and isolation.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces contact resistance for both device types by increasing surface area and enabling self-aligned doping, preserving trench integrity and preventing shorts, thus improving performance in semiconductor fabrication.

Implementation Method 1

forming a sacrificial epitaxial capping layer that is used to mitigate erosion of the TS etch and open up a wider volume at the bottom of the trench

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

implanting dopant into S/D regions after high temperature processing and using laser spike anneal (LSA) to activate higher doping quantities

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 3

using laser spike anneal (LSA) to activate higher doping quantities

Methodology Applied
Scientific EffectLaser heating: Laser

Data Source

PatentUS10741556B2Self-aligned sacrificial epitaxial capping for trench silicide
Publication Date: 2020.08.11 GLOBALFOUNDRIES US INC
  • US10741556B2 patent drawing
  • US10741556B2 patent drawing
  • US10741556B2 patent drawing

AI summary

A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include a Si fin formed in a PFET region; a pair of Si fins formed in a NFET region; epitaxial S/D regions formed on ends of the Si fins; a replacement metal gate formed over the Si fins in the PFET and NFET regions; metal silicide trenches formed over the epitaxial S/D regions in the PFET and NEFT regions; a metal layer formed over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region, wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view.