Sacrificial Gate Capping Layer for Plasma Etch Contact Opening
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor plasma processing techniques cause damage to cap layers and erosion of spacers on gate sidewalls during the opening of high aspect ratio contact holes, leading to uncontrolled variations in device electrical performance and yield loss.
Innovation Solution
A method involving a sacrificial gate capping layer is formed on the substrate during plasma etching, with controlled plasma etch processes to protect the underlying material, including forming a sacrificial gate capping layer on the substrate and repeating etch processes to gradually remove dielectric and spacer layers without exposing the source/drain contact regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a dry etch process is used to open contact holes, then the etching speed and aspect ratio capability are improved, but damage to cap layers and erosion of spacers occur
Solution Approach 1:
A sacrificial capping layer is introduced as an intermediary protective element between the plasma etch process and the underlying cap layers/spacers. This sacrificial layer absorbs the harmful ion bombardment and chemical effects, preventing damage to the critical device structures while allowing the etch process to proceed at high speed through the interlayer dielectric.
Solution Approach 2:
The sacrificial capping layer is deposited in advance before the plasma etch process to provide pre-protection to the cap layers and spacers. This preliminary protective action ensures that when the aggressive etch process occurs, the damage-prone structures are already shielded, eliminating the need for post-etch repair or rework.
2Productivity
If the plasma etch process is made more aggressive to increase productivity, then the etching rate is improved, but device layer damage increases
Solution Approach 1:
The sacrificial capping layer serves as a mediator that allows the plasma etch process to operate at high power and speed settings without transferring the full brunt of the process aggression to the device layers. This enables manufacturers to maintain high productivity while preserving manufacturing precision through the protective intermediary layer.
Solution Approach 2:
The sacrificial capping layer is designed as a disposable protective element that is intentionally consumed during the etch process. This thin, sacrificial material is deposited specifically to be removed along with the dielectric, providing temporary but effective protection during the high-speed etch operation without requiring complex protective structures.
3Quantity of substance
If the plasma etch process is used to remove dielectric material, then the material removal efficiency is improved, but uncontrolled variations in device electrical performance occur
Solution Approach 1:
The sacrificial capping layer acts as a protective intermediary that prevents direct plasma exposure of the cap layers and spacers during dielectric removal. This mediation ensures uniform and controlled etching of the dielectric material without the uncontrolled damage variations that would otherwise occur, leading to consistent device electrical performance across the wafer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents damage to semiconductor regions during plasma etching, reducing corner loss and maintaining device integrity, thereby improving electrical performance and yield.
Implementation Method 1
a dry etch process such as reactive Ion etching (RIE) may be used to open contacts
Implementation Method 2
the plasma etch process possesses a plasma source that generates a sea of ions that accelerate in a manner that causes ion bombardment against sensitive device layers
Data Source
AI summary
A method including providing a substrate including metal gate stacks and source/drain contact regions in alternating arrangement along a surface of the substrate, each of the source/drain contact regions being recessed within a respective opening between adjacent metal gate stacks such that source/drain contact regions provide a bottom of the opening and adjacent metal gate stacks provide sidewalls, and a dielectric covering the substrate such that the dielectric fills each opening. The substrate is exposed to an initial plasma etch process to remove a first portion of the dielectric from each opening down to a first depth, and a sacrificial gate capping layer is formed on the substrate while leaving each of the openings uncovered. The substrate is exposed to another plasma etch process to remove the sacrificial gate capping layer while removing a second portion of the dielectric from each opening down to a second depth.