Sacrificial Gate Planarization to Suppress CMP Dishing
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing three-dimensional designs like FinFETs and GAA FETs due to issues such as dishing problems during chemical-mechanical polishing (CMP) operations, which affect the planarity and isolation properties of cap insulating layers.
Innovation Solution
A method is introduced to suppress dishing problems during CMP by employing specific CMP processes with controlled down forces and slurry compositions, along with precise endpoint detection techniques to ensure uniform planarization of dielectric layers, thereby improving the isolation properties of cap insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical-mechanical polishing (CMP) is used to planarize dielectric layers, then planarity is improved, but dishing problems occur affecting cap insulating layer quality
Solution Approach 1:
The patent modifies CMP process parameters including using a two-step CMP approach with different down forces and slurry compositions. The first CMP step uses a higher down force to remove excess dielectric material, while the second step uses a lower down force to achieve final planarity without causing dishing. This parameter optimization resolves the contradiction between achieving planarity and avoiding dishing damage.
2Productivity
If higher down force is applied during CMP to improve planarization efficiency, then productivity is improved, but dishing problems worsen
Solution Approach 1:
The patent divides the CMP process into two separate steps: a first CMP step with higher down force for efficient material removal, and a second CMP step with lower down force for precise planarity control. This segmentation allows each step to optimize for its specific function, maintaining productivity while preventing dishing in the final planarized layer.
3Manufacturing precision
If precise endpoint detection is implemented to improve planarity, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent implements endpoint detection during CMP operations to monitor when the polishing process should stop. This feedback mechanism ensures that the CMP process terminates at the optimal point, achieving uniform planarization without over-polishing that could cause dishing. The endpoint detection provides real-time control to maintain precision while managing process complexity through automated monitoring.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the planarity and isolation properties of cap insulating layers, reducing manufacturing defects and costs associated with dishing, thus improving the reliability and performance of FinFET and GAA FET devices.
Implementation Method 1
dishing problems during chemical-mechanical polishing (CMP) operations
Implementation Method 2
chemical-mechanical polishing (CMP) operations
Implementation Method 3
The sacrificial gate structures and the first dielectric layer are etched to expose upper portions of the fin structures
Data Source
AI summary
In a method of manufacturing a semiconductor device, a sacrificial gate structure including sacrificial gate electrode is formed over a substrate. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The recessing the first dielectric layer comprises a first etching operation and a second etching operation using a different etching as from the first etching operation.