Sacrificial Gate CMP Sequencing for Planar Dielectric Recess
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing three-dimensional designs such as FinFETs and GAA FETs due to issues like dishing during chemical mechanical polishing (CMP) operations, which affect the planarization of dielectric layers and the isolation properties of cap insulating layers.
Innovation Solution
A method is developed to suppress dishing problems during CMP by using specific CMP processes and slurry compositions that selectively etch different materials, ensuring uniform planarization and improved isolation properties of the cap insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional CMP processes are used for planarization, then manufacturing process is simple, but dishing occurs affecting planarity and isolation properties
Solution Approach 1:
The CMP process is divided into multiple sequential steps with different slurries: first CMP step removes dielectric material, second CMP step removes sacrificial gate material, and third CMP step performs final planarization. Each step uses optimized slurry composition and parameters to address specific planarity requirements without causing dishing.
Solution Approach 2:
The patent modifies CMP process parameters including slurry composition (pH, abrasive particle size and type), downforce, and rotation speed across different CMP steps. These parameter changes enable selective material removal and prevent dishing while achieving the required planarity for subsequent processing steps.
2Manufacturing precision
If conventional CMP slurries are used, then manufacturing cost is low, but dishing affects isolation properties of cap insulating layer
Solution Approach 1:
Different slurry compositions are applied at different stages to address local requirements: the first slurry is optimized for dielectric layer removal, the second for sacrificial gate material removal, and the third for final planarization. This localized optimization ensures proper isolation properties without unnecessary complexity in all steps.
Solution Approach 2:
The patent implements continuous planarization through multiple CMP steps that maintain consistent quality standards throughout the manufacturing process. Each step builds upon the previous one to progressively achieve the required planarity and isolation properties, preventing defects that would require costly rework.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the planarity and isolation properties of semiconductor devices, reducing manufacturing defects and costs associated with CMP operations.
Implementation Method 1
chemical mechanical polishing (CMP) operations
Implementation Method 2
slurry compositions that selectively etch different materials
Data Source
AI summary
In a method of manufacturing a semiconductor device, a sacrificial gate structure is formed over a substrate. The sacrificial gate structure includes a sacrificial gate electrode. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed while a lower portion of the sacrificial gate structure is embedded in the first dielectric layer. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The sacrificial gate electrode is removed.