Sacrificial Gate Etching Cycles for High-Aspect-Ratio Filling
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Solution Overview
Problem
The increasing aspect ratio of sacrificial gate structures in semiconductor manufacturing poses challenges in filling the gate electrode layer during the replacement gate process, particularly for gate structures near dielectric fins.
Innovation Solution
A method involving a cyclic operation of etching and passivation is used to form sacrificial gate structures, with pulsing power supply in the passivation process to prevent lateral over etching and improve the quality of contact features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given chip area, but the aspect ratio of sacrificial gate structures increases causing difficulties in filling gate electrode layer
Solution Approach 1:
The patent segments the continuous etching process into multiple cyclic steps, alternating between etching and passivation. This segmentation allows controlled removal of sacrificial gate material while preventing unwanted lateral etching, enabling precise formation of high aspect ratio gate structures that can be properly filled with gate electrode material.
Solution Approach 2:
The patent employs periodic cyclic etching and passivation actions to selectively remove sacrificial gate material. The periodic passivation steps deposit protective layers during specific intervals, preventing lateral over-etching while allowing vertical etching progress, thus maintaining the integrity of high aspect ratio gate structures for subsequent electrode filling.
2Ease of manufacture
If conventional continuous etching is used to form sacrificial gate structures, then the etching process is simple, but lateral over etching occurs near high-k dielectric features reducing manufacturing precision
Solution Approach 1:
The patent applies preliminary passivation action during the etching process by depositing protective layers on exposed surfaces before lateral over-etching can occur. This preliminary protection at high-k dielectric interfaces prevents dimensional inaccuracies while maintaining overall process simplicity through cyclic repetition.
Solution Approach 2:
The patent introduces passivation layers as intermediary protective barriers between the etching chemistry and the sacrificial gate structures near high-k dielectric features. These intermediary layers selectively prevent lateral etching attacks while allowing the etching process to continue elsewhere, maintaining both precision and manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents over etching of the sacrificial gate electrode near high-k dielectric features, enhancing the filling windows for replacement gate structures and improving device performance by enlarging the volume of source/drain regions.
Implementation Method 1
performing a cyclic process to expose a top surface of the semiconductor fin, wherein the cyclic process includes two or more cycles of: performing an etching process; and performing a passivation process
Implementation Method 2
performing a passivation process
Data Source
AI summary
A cyclic process including an etching process, a passivation process, and a pumping out process is provided to prevent over etching of the sacrificial gate electrode, particularly when near a high-k dielectric feature. The cyclic process solves the problems of failed gate electrode layer at an end of channel region and enlarges filling windows for replacement gate structures, thus improving channel control. Compared to state-of-art solutions, embodiments of the present disclosure also enlarge volume of source/drain regions, thus improving device performance.