Sacrificial Gate Fabrication for High-k Dielectric Control
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits leads to increased complexity and power dissipation, necessitating the development of low power dissipation devices like CMOS with high-k gate dielectric and metal gate electrodes, while maintaining precise control over dielectric layer thickness and surface roughness during fabrication.
Innovation Solution
A method involving the formation of a sacrificial gate layer, patterning, spacer formation, interlayer dielectric filling, sacrificial gate removal, and subsequent dielectric layer processing to achieve precise control over dielectric layer thickness and surface roughness, including the use of high-k gate dielectric and metal gate electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but power dissipation increases
Solution Approach 1:
The patent changes the material parameters of the gate electrode from conventional polysilicon to metal materials with different electrical and physical properties. This parameter change enables lower resistance and reduced power dissipation in scaled-down devices, allowing continued scaling while managing power consumption.
Solution Approach 2:
The patent employs composite material structures including metal gate electrodes combined with high-k dielectric materials. This composite approach optimizes both the electrical performance for low power dissipation and the manufacturing compatibility for high productivity in scaled devices.
2Reliability
If high-k gate dielectric and metal gate electrode are used to improve device performance, then device performance is improved, but fabrication process complexity increases
Solution Approach 1:
The patent applies preliminary actions by forming the metal gate electrode and high-k dielectric structure before final transistor activation. This sequencing allows the complex materials to be integrated early in the process when the substrate is most accessible, simplifying subsequent processing steps.
Solution Approach 2:
The patent applies local quality by implementing metal gate electrodes selectively in specific device regions while maintaining compatibility with standard CMOS processes in other areas. This localized approach improves device performance where needed without requiring complete process overhaul.
3Manufacturing precision
If dielectric layer thickness is precisely controlled during fabrication, then manufacturing precision is improved, but process difficulty increases
Solution Approach 1:
The patent replaces mechanical thickness control methods with atomic-layer deposition techniques that use self-limiting chemical reactions. This substitution enables precise dielectric layer thickness control at the atomic level, achieving manufacturing precision without proportionally increasing process difficulty.
Solution Approach 2:
The patent changes the deposition parameters and material composition to achieve precise thickness control. By adjusting deposition conditions and using materials with favorable properties, the process achieves high precision while maintaining reasonable manufacturing complexity.
Data Source
AI summary
A method for manufacturing the integrated circuit device comprises providing a substrate having a first region, a second region, and a third region. A first gate stack, a second gate stack, and a third gate stack are formed over the substrate in the first region, the second region, and the third region, respectively. The first gate stack, the second gate stack, and the third gate stack comprise a sacrificial layer over a first dielectric layer. The first gate stack and the second gate stack are removed and a second dielectric layer is formed in the first region and the second region. The portion of second dielectric layer in the first region is transformed into a third dielectric layer by a treatment.