Sacrificial Gate Electrode Profile for FinFET Height Control
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Solution Overview
Problem
In advanced FinFET devices, controlling the height of the recessed metal gate structure is challenging due to variations in metal structures and threshold voltages, which can lead to insufficient electric separation between the metal gate electrode and adjacent contacts or damage to the underlying fin structure during the gate recess etching process.
Innovation Solution
The profile of the sacrificial gate electrode is adjusted to have a narrow portion above the fin top area, with controlled etching conditions to ensure a uniform etching rate, resulting in a metal gate structure with a desired height and preventing damage to the fin structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional gate recess etching is performed on metal gate structures with variations in structure and threshold voltage, then the etching process can be simplified, but the height control of the recessed metal gate structure becomes insufficient and damage to the fin structure may occur
Solution Approach 1:
A sacrificial gate electrode is introduced as an intermediary element between the fin structure and the metal gate structure. This sacrificial electrode serves as a protective placeholder during the gate recess etching process, allowing the etch to proceed without directly exposing and potentially damaging the fin structure. The sacrificial electrode is later removed after serving its protective function, enabling precise height control of the metal gate structure while maintaining process simplicity.
2Ease of manufacture
If conventional gate recess etching is performed without additional protective measures, then the manufacturing process remains simple, but damage to the underlying fin structure may occur during etching
Solution Approach 1:
The sacrificial gate electrode is formed beforehand as a protective cushioning layer over the fin structure. This electrode absorbs the harmful effects of the gate recess etching process, preventing direct contact between the etchant and the fin structure. By providing this prior protective measure, the process maintains simplicity while effectively preventing fin structure damage during etching.
3Manufacturing precision
If the sacrificial gate electrode profile is adjusted to include a narrow portion, then the metal gate structure height can be precisely controlled, but the etching process becomes more complex
Solution Approach 1:
The sacrificial gate electrode is designed with local quality variation, featuring a narrow portion at a specific location rather than a uniform profile throughout. This localized profile modification creates a controlled etching stop point that enables precise height control of the metal gate structure. By applying the profile complexity only where needed (local quality) rather than throughout the entire structure, the solution achieves precision control while minimizing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise control of the metal gate structure height, improving device performance and yield by ensuring consistent etching rates across different metal gate structures and preventing damage during the gate recess etching process.
Implementation Method 1
The polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure... the patterning the polysilicon layer comprises a plasm dry etching using HBr gas and Cl2 gas
Implementation Method 2
the gate dielectric layer and the gate electrode layer are recessed, and an insulating cap layer is formed over the recessed gate dielectric layer and the recessed gate electrode layer
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.


