Sacrificial Gate Cleaning to Remove Residue Without Over-Etching
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Solution Overview
Problem
The existing etching processes for semiconductor device manufacturing often require long over-etching times to remove sacrificial layers, leading to yield loss defects due to damage to the bottom layers.
Innovation Solution
A method involving a hydrophilic treatment and a hydrophobic treatment is applied after the initial etching process to remove the sacrificial layer, utilizing surface modification processes with acidic oxidants and fluorinated acids to enhance bubble mobility and prevent etching blockages, allowing for reduced over-etching time and minimizing damage to underlying layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If long over-etching time is used to completely remove the sacrificial layer, then the sacrificial layer can be fully removed, but the bottom layer below the sacrificial layer is damaged causing yield loss
Solution Approach 1:
The patent segments the sacrificial layer removal process into two distinct stages: a first etching process that removes the majority of the sacrificial layer, and a second etching process with different etching conditions that removes the remaining residue. This segmentation allows each process to be optimized independently, preventing damage to the bottom layer while ensuring complete removal.
Solution Approach 2:
The patent changes etching parameters between the two etching processes. The first etching process uses initial etching conditions, while the second etching process uses different etching conditions (such as adjusted etchant concentration, temperature, or time). This parameter change enables precise control over the etching depth and rate, allowing complete removal of the sacrificial layer without damaging the underlying bottom layer.
2Manufacturing precision
If long etching time is used to ensure complete removal, then residue is eliminated, but the process time increases reducing productivity
Solution Approach 1:
The patent divides the etching process into two sequential steps: a first etching process that rapidly removes the bulk of the sacrificial layer, and a second etching process that efficiently removes the remaining residue. This segmentation prevents the need for excessively long single-stage etching, thereby reducing total process time while ensuring complete removal.
Solution Approach 2:
By changing etching parameters between the two processes (such as etchant composition, temperature, or time duration), the patent optimizes each stage for its specific purpose. The first process is optimized for high removal rate, while the second is optimized for complete residue elimination, achieving both efficiency and completeness without excessive total time.
3Productivity
If aggressive etching is used to speed up the process, then productivity increases, but damage to the bottom layer increases causing yield loss
Solution Approach 1:
The patent segments the etching process into two stages with different aggressiveness levels. The first etching process uses more aggressive conditions to achieve high removal speed for the bulk material, while the second etching process uses milder conditions to safely remove the remaining residue without damaging the bottom layer. This segmentation allows high productivity while protecting the underlying structure.
Solution Approach 2:
The patent changes etching parameters between processes to balance speed and safety. The first process uses parameters optimized for high etching rate (such as higher etchant concentration or temperature), while the second process uses parameters optimized for selectivity and safety (such as lower concentration or temperature), preventing bottom layer damage while maintaining overall productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces defects and increases chip yield by preventing bubble-induced etching blockages and shortening the removal time of sacrificial layers, thereby protecting the bottom layers and improving manufacturing efficiency.
Implementation Method 1
performing a hydrophilic treatment and a hydrophobic treatment to remove a residue of the sacrificial layer
Implementation Method 2
performing a hydrophilic treatment and a hydrophobic treatment to remove a residue of the sacrificial layer
Implementation Method 3
utilizing surface modification processes with acidic oxidants and fluorinated acids
Implementation Method 4
utilizing surface modification processes with acidic oxidants and fluorinated acids
Data Source
AI summary
A method for a clean procedure during manufacturing a semiconductor device, includes: providing a patterned sacrificial gate structure including a gate dielectric and a sacrificial layer; wherein the patterned sacrificial gate structure is embedded in a dielectric layer and an upper surface of the sacrificial layer is exposed; performing a first etching process to remove the sacrificial layer; and performing a hydrophilic treatment and a hydrophobic treatment to remove a residue of the sacrificial layer.