Self-Aligned Double Pattern Formation Using Sacrificial Layers
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Solution Overview
Problem
Current methods for forming self-aligned double patterns in semiconductor manufacturing face challenges such as non-planar surfaces, electrical connection issues, and complexity in dielectric pattern formation, particularly due to limitations in photoresist sensitivity to short wavelengths and the need for multiple sacrificial processes.
Innovation Solution
A method involving the use of sacrificial layers and mask patterns to form self-aligned double patterns, where sacrificial layers are etched and planarized to enable precise etching of underlying layers, preventing loading effects and allowing for patterns twice as integrated as the resolution limit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional photolithography with short wavelength light sources is used, then resolution improves, but photoresist sensitivity deteriorates due to lack of available photoresist that can absorb short wavelength light and enable chemical amplification
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary material between the photoresist pattern and the underlying layer. This sacrificial layer has specific etch selectivity that allows it to be selectively removed to form spaces, enabling the double pattern formation without requiring photoresist that can directly absorb short wavelength light for the desired resolution
Solution Approach 2:
The patent segments the patterning process into multiple steps: first forming a photoresist pattern, then using a sacrificial layer to create additional spaces, and finally forming the complete double pattern. This segmentation allows each step to be optimized independently, overcoming the limitation of photoresist sensitivity
2Manufacturing precision
If first conventional method is used to form metal patterns, then self-aligned double pattern is achieved, but planar surface formation deteriorates resulting in non-planar surfaces
Solution Approach 1:
The sacrificial layer acts as a mediator that enables precise pattern alignment through self-alignment mechanisms while maintaining surface planarity. By using the sacrificial layer's etch selectivity and controlled removal, the method achieves both alignment precision and surface flatness that the first conventional method failed to provide
3Shape
If second conventional method is used to form interconnection patterns, then planarization is achieved, but electrical connection deteriorates due to impeded connection between second interconnection pattern and substrate
Solution Approach 1:
The patent extracts the planarization function from the interconnection pattern formation process itself. By using a separate sacrificial layer removal process that creates spaces rather than adding thick insulating layers, the method maintains electrical connection pathways while achieving the necessary surface planarity for subsequent processing
4Quantity of substance
If third conventional method is used for pitch reduction, then dielectric layer pattern density is doubled, but process complexity increases due to multiple sacrificial processes and preclusion of dielectric pattern formation
Solution Approach 1:
The patent merges the sacrificial layer function with the space formation function into a single integrated process. The sacrificial layer is formed, patterned, and selectively removed in one coordinated sequence, achieving doubled pattern density without requiring multiple separate sacrificial processes, thereby reducing overall process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of self-aligned double patterns with uniform profiles and increased integration density, overcoming the limitations of existing techniques by ensuring planar surfaces and preventing electrical connection impediments.
Implementation Method 1
Etching may be performed using the second insulating layer pattern as an etch mask
Implementation Method 2
A planarization process may be performed on the interconnection material layer
Data Source
AI summary
Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the tops of the first mask patterns and the second mask patterns have planar surfaces. After the planarization of the sacrificial layer, the remaining the sacrificial layer may be removed by an ashing process.