Sacrificial Nanoribbon Gate Structure for Uniform Workfunction Control
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Solution Overview
Problem
The fabrication of high-performing and reliable integrated circuit (IC) devices with gate-all-around field-effect transistors (GAA FETs) is challenged by insufficient or non-uniform distribution of workfunction metals, leading to degraded performance and reliability due to parasitic capacitances and non-uniform drive current.
Innovation Solution
Employing a sacrificial or dummy nanoribbon to ensure uniform gate metal distribution and thickness over and under nanoribbon channels, with the dummy nanoribbon later removed to maintain symmetry and uniformity, thereby allowing for reduced gate height and lower parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If gate metal height and volume are reduced to minimize parasitic capacitances, then parasitic capacitances are minimized, but adequate quantities of gate metal may be insufficient to properly set transistor conduction over wide ranges of gate bias
Solution Approach 1:
The gate electrode is segmented into multiple thickness regions: a first thickness over the nanoribbon channel and a second thickness between nanoribbons. This segmentation allows different portions of the gate metal to serve different functions - the thinner region minimizes parasitic capacitance while the thicker region ensures adequate workfunction metal quantity for proper transistor conduction control across wide gate bias ranges.
Solution Approach 2:
Different thicknesses of gate metal are applied to different locations: a reduced thickness over the channel region to minimize parasitic capacitance, and increased thickness between nanoribbon regions to ensure adequate quantities of workfunction metal for setting transistor conduction. This local quality variation resolves the contradiction between minimizing parasitic effects and ensuring sufficient metal quantity for reliable operation.
2Object-affected harmful factors
If gate metal thickness is reduced over nanoribbon channels, then parasitic capacitances are minimized, but uniform distribution of workfunction metals may be compromised
Solution Approach 1:
The gate electrode structure is segmented with a first thickness region over the nanoribbon channel and a second thickness region between nanoribbons. This segmentation enables the workfunction metal to be distributed uniformly in the critical between-nanoribbon regions while maintaining reduced thickness over the channel, thus minimizing parasitic capacitance without compromising workfunction metal uniformity where it is most needed.
Solution Approach 2:
The gate electrode thickness is varied in the vertical dimension to achieve uniform workfunction metal distribution. By implementing different thicknesses at different vertical positions (over channel versus between nanoribbons), the patent achieves both minimized parasitic capacitance and uniform workfunction metal distribution, resolving the contradiction through dimensional variation.
3Reliability
If gate-all-around structure is implemented to improve transistor performance, then device performance is enhanced, but fabrication complexity increases due to managing uniform threshold voltages
Solution Approach 1:
The gate electrode is segmented into distinct thickness regions that can be fabricated using standard deposition and etching processes. The first thickness over the channel and the second thickness between nanoribbons are created through controlled deposition followed by selective removal, leveraging existing manufacturing capabilities to achieve the complex gate-all-around structure without proportionally increasing fabrication complexity.
Solution Approach 2:
The gate electrode is initially deposited with a uniform thickness that provides adequate workfunction metal coverage, and then selective removal is performed to create the thinner region over the channel. This preliminary action of depositing uniform metal first ensures that adequate quantities of workfunction metal are present throughout, and subsequent selective etching creates the optimized thickness profile, simplifying the overall fabrication process.
Data Source
AI summary
Integrated circuit (IC) devices having gate-all-around field-effect transistors with nanoribbon channels through gate electrodes. An IC device has a stack of nanoribbon channels through a gate electrode, and the gate electrode has uniform gate thicknesses of gate metal and dielectric layers between, over, and under each of the nanoribbons. The nanoribbons extend between pairs of gate spacers to couple source and drain bodies, with pairs of matching gate spacers over and under each of the nanoribbons. A pair of second gate spacers are on and over an uppermost pair of the first gate spacers. A sacrificial cap layer is deployed over an uppermost of the channel layers during processing, and end portions of cap layer are retained as the second gate spacers.