Self-Aligned Bipolar Transistor Using Sacrificial Nitride Emitter
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Solution Overview
Problem
The existing methods for manufacturing self-aligned bipolar transistors using sacrificial nitride emitters require complex chemical mechanical polishing (CMP) processes, which limit reproducibility and compatibility with BiCMOS technology due to the need for precise control to avoid damaging the CMOS polysilicon gate region.
Innovation Solution
A simplified method involving physical vapor deposition of an oxide layer over the silicon nitride emitter, followed by etching to form an emitter window and creating a polysilicon emitter structure without using CMP, utilizing anisotropic PVD and isotropic wet etch processes to remove the sacrificial nitride emitter, ensuring compatibility with BiCMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing (CMP) is used to planarize the sacrificial nitride emitter, then the top of the emitter can be exposed, but the process complexity increases and compatibility with BiCMOS technology is limited
Solution Approach 1:
The patent extracts and removes the problematic CMP step from the manufacturing process. Instead of using CMP to expose the sacrificial nitride emitter, the invention uses a self-aligned etch process where the oxide layer is selectively removed to expose the emitter, eliminating the need for mechanical polishing and reducing process complexity
Solution Approach 2:
The patent replaces the mechanical CMP process with a chemical etching process. The oxide layer is removed through chemical means (etching) rather than mechanical means (polishing), which avoids the complexity and compatibility issues associated with CMP while achieving the same goal of exposing the sacrificial emitter
2Manufacturing precision
If CMP is used to expose the sacrificial nitride emitter, then the emitter can be accessed, but reproducibility is limited due to the need for precise control
Solution Approach 1:
The patent implements a self-aligned process where the etch holes are automatically positioned relative to the sacrificial emitter through the oxide layer pattern. This self-alignment mechanism eliminates the need for precise manual control during the exposure step, improving reproducibility while maintaining precision
Solution Approach 2:
The patent performs preliminary patterning of the oxide layer before the etching step. The oxide is deposited and patterned in advance to define the exact locations where etch holes will be formed, ensuring that the subsequent etching process automatically achieves the correct alignment without requiring precise real-time control
3Manufacturing precision
If CMP is used in the manufacturing process, then the sacrificial emitter can be exposed, but compatibility with BiCMOS technology is compromised due to potential damage to CMOS polysilicon gate region
Solution Approach 1:
The patent removes the CMP step from the process flow, eliminating the source of potential damage to CMOS polysilicon gates. By using chemical etching instead of mechanical polishing, the process becomes compatible with BiCMOS technology while still achieving the necessary emitter exposure
Solution Approach 2:
The patent uses an oxide layer as an intermediary protective layer between the processing steps and the underlying structures. This oxide layer can be selectively removed through etching without affecting the CMOS polysilicon gate region, enabling safe processing in BiCMOS technology
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces process complexity, enhances reproducibility, and improves compatibility with BiCMOS technology by eliminating the need for CMP, while maintaining low parasitic capacitances and resistances, thereby achieving high radio frequency (RF) performance.
Implementation Method 1
a physical vapor deposition oxide layer is deposited over the silicon nitride sacrificial emitter using a physical vapor deposition process
Implementation Method 2
The physical vapor deposition oxide layer is then etched away from the side walls of the sacrificial emitter
Data Source
AI summary
A system and method are disclosed for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter. An active region of a transistor is formed and a silicon nitride sacrificial emitter is formed above the active region of the transistor. Then a physical vapor deposition oxide layer is deposited over the silicon nitride sacrificial emitter using a physical vapor deposition process. The physical vapor deposition oxide layer is then etched away from the side walls of the sacrificial emitter. The sacrificial emitter is then etched away to form an emitter window. Then a polysilicon emitter structure is formed in the emitter window. The self aligned bipolar transistor architecture of the invention is compatible with BiCMOS technology.