Sacrificial Probe Pad Layout for Higher Interconnect Routing Area
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Solution Overview
Problem
Conventional semiconductor packaging technologies face challenges in maximizing interconnect routing area due to non-removable probe pads, which restrict the utilization of underlying metallization layers for conductive vias, leading to unutilized space in interconnect structures.
Innovation Solution
The integration of a sacrificial probe pad that can be removed after testing, allowing conductive vias to access underlying metallization layers, thereby increasing the interconnect routing area and enabling more efficient packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-removable probe pads are used for testing, then testing functionality is achieved, but interconnect routing area is reduced due to unutilized underlying metallization layers
Solution Approach 1:
The probe pad is designed as a sacrificial structure that is removed after testing is completed. The removal process recovers the underlying metallization layer area, allowing it to be utilized for conductive vias and interconnect routing. This transforms the permanently occupied space into usable routing area, resolving the contradiction between maintaining testing functionality and maximizing routing area.
Solution Approach 2:
The probe pad structure is segmented into a removable upper portion and the underlying metallization layer. The upper portion serves the testing function temporarily, then is separated and removed, while the lower portion remains for interconnect routing. This segmentation allows the same spatial location to serve different functions at different stages of the manufacturing process.
2Ease of operation
If probe pads occupy underlying metallization layers, then testing access is provided, but space for conductive vias and bond pads is lost
Solution Approach 1:
Testing is performed as a preliminary action before final packaging. The probe pad provides temporary access for this preliminary testing step, then is removed to allow subsequent actions (forming conductive vias and bond pads) to utilize the previously occupied space. This sequencing resolves the contradiction by allocating space temporarily for testing, then permanently for conductive features.
Solution Approach 2:
The probe pad acts as an intermediary structure that enables testing access without permanently blocking the underlying metallization. It mediates between the need for testing and the need for routing area by providing temporary access during testing, then being removed to allow full utilization of the space for its intended purpose.
3Area of stationary object
If sacrificial probe pads are removed after testing, then interconnect routing area is enhanced, but additional etch processes are required
Solution Approach 1:
The etch process used to remove the sacrificial probe pad is designed to serve multiple functions: it removes the probe pad material, defines the opening for the conductive via, and prepares the surface for subsequent metallization. By making the etch process multi-functional, the patent reduces the need for separate dedicated removal steps, thereby minimizing the increase in process complexity while achieving the goal of enhancing routing area.
Data Source
AI summary
An embodiment is a method including a first dielectric layer over a first substrate, the first dielectric layer having a first metallization pattern therein. The method also includes forming a second dielectric layer over the first dielectric layer and the first metallization pattern. The method also includes forming a sacrificial pad over and extending into the second dielectric layer, the sacrificial pad being electrically coupled to a first conductive feature in the first metallization pattern. The method also includes performing a circuit probe test on the sacrificial pad. The method also includes after performing the circuit probe test, performing an etch process, the etch process removing the sacrificial pad.