Sacrificial Probe Pad Layout for Higher Interconnect Routing
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Solution Overview
Problem
Conventional semiconductor packaging techniques face challenges in maximizing interconnect routing area due to the unutilized space beneath probe pads, which are typically non-removable and obstruct underlying metallization layers from being reached by conductive vias.
Innovation Solution
Incorporation of a sacrificial probe pad that is removable after testing, allowing underlying metallization layers to be accessed by conductive vias, thereby increasing the interconnect routing area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional non-removable probe pads are used, then testing can be performed, but the space beneath probe pads remains unutilized and obstructs access to underlying metallization layers
Solution Approach 1:
The probe pad is extracted as a removable component rather than a permanent structure. The method involves forming a probe pad over an opening in the passivation layer, performing circuit probe tests, and then removing the probe pad to expose the underlying metallization layer, thereby converting a permanent obstruction into a temporary testing element that can be extracted after use.
Solution Approach 2:
The probe pad is formed and positioned in advance before the actual interconnect routing is completed. The probe pad is created over the opening in the passivation layer prior to forming the conductive vias, allowing testing to occur before the underlying metallization needs to be accessed, and then the probe pad is removed to enable subsequent via formation.
2Area of stationary object
If probe pads are made removable to increase routing area, then access to underlying metallization layers is enabled, but additional process steps are required
Solution Approach 1:
The probe pad serves as an intermediary element that temporarily occupies the opening during testing but is designed to be removed without damaging underlying structures. The probe pad is formed as a separate, removable component that mediates between the need for surface testing and the need for subs metallization access, being removed after testing to enable via formation.
Solution Approach 2:
The physical state of the probe pad is changed from present to removed based on the testing timeline. The probe pad exists during the testing phase and is subsequently removed through etching or other removal processes, changing its presence parameter from 1 (present) to 0 (removed) to enable access to the underlying metallization layer.
3Area of stationary object
If sacrificial probe pads are used, then interconnect routing area is maximized, but the probe pad material must be completely removed without damaging underlying structures
Solution Approach 1:
The probe pad is formed using composite material layers including a solder material layer and a seed layer with different etch selectivities. The solder material layer (e.g., tin-based alloy) and seed layer (e.g., copper) have distinct chemical properties that allow selective removal of the probe pad material through etching processes without damaging the underlying metallization or substrate structures.
Data Source
AI summary
An embodiment is a method including a first dielectric layer over a first substrate, the first dielectric layer having a first metallization pattern therein. The method also includes forming a second dielectric layer over the first dielectric layer and the first metallization pattern. The method also includes forming a sacrificial pad over and extending into the second dielectric layer, the sacrificial pad being electrically coupled to a first conductive feature in the first metallization pattern. The method also includes performing a circuit probe test on the sacrificial pad. The method also includes after performing the circuit probe test, performing an etch process, the etch process removing the sacrificial pad.