Sacrificial S/D Layer for Transistor Contact Resistance
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Solution Overview
Problem
In transistor devices, such as MOSFETs, undesired resistance is a significant issue due to high contact resistance between source/drain semiconductor material and metal contact structures, which limits drive currents and performance, particularly in scaled transistors where the reduced contact area exacerbates this problem.
Innovation Solution
The implementation of a sacrificial source/drain (S/D) layer that is deposited prior to epitaxial growth and subsequently etched away to increase the contact area between the semiconductor material and metal, allowing for contact deposition under and between the epitaxial material, thereby reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source/drain contact structures are used with direct metal contact to semiconductor material, then the structure is simple and manufacturing is easier, but the contact area is small leading to high contact resistance
Solution Approach 1:
An epitaxial source/drain layer is introduced as an intermediary between the metal contact structure and the semiconductor material. This intermediate layer grows epitaxially from the semiconductor substrate and provides a larger contact area for the metal, thereby reducing contact resistance while maintaining structural integrity and compatibility with existing fabrication processes.
2Productivity
If transistor size is scaled down to improve integration density, then more transistors can be packed, but the contact area is reduced exacerbating contact resistance
Solution Approach 1:
The contact structure transitions from a planar two-dimensional contact interface to a three-dimensional structure where the epitaxial source/drain layer extends vertically and laterally. This dimensional expansion provides increased contact area in the vertical dimension while maintaining the scaled-down lateral footprint, thereby reducing contact resistance without compromising integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the contact area between the metal and semiconductor material, leading to lower contact resistance and improved device performance by providing a straighter conduction path and reducing parasitic resistance.
Implementation Method 1
The sacrificial source/drain layer is etched away to increase the contact area between the semiconductor material and metal
Implementation Method 2
epitaxial growth and subsequently etched away to increase the contact area between the semiconductor material and metal
Data Source
AI summary
Integrated circuit structures including increased transistor source/drain (S/D) contact area using a sacrificial S/D layer are provided herein. The sacrificial layer, which includes different material from the S/D material, is deposited into the S/D trenches prior to the epitaxial growth of that S/D material, such that the sacrificial layer acts as a space-holder below the S/D material. During S/D contact processing, the sacrificial layer can be selectively etched relative to the S/D material to at least partially remove it, leaving space below the S/D material for the contact metal to fill. In some cases, the contact metal is also between portions of the S/D material. In some cases, the contact metal wraps around the epi S/D, such as when dielectric wall structures on either side of the S/D region are employed. By increasing the S/D contact area, the contact resistance is reduced, thereby improving the performance of the transistor device.