Sacrificial SiGe Fin Integration for Sub-Lithographic Pitch Control
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Solution Overview
Problem
The challenge is to increase the density of semiconductor devices using fins while maintaining desirable electrical characteristics and efficiently integrating them with planar transistors, as existing technologies face limitations in minimum fin spacing and facet control.
Innovation Solution
The method involves forming a sacrificial silicon germanium (SiGe) fin over a silicon seed layer, growing epitaxial silicon on its sides, and then removing the SiGe fin to create two silicon fins with controlled width and spacing, allowing for sub-lithographic pitch and reduced faceting, thereby doubling the density and improving integration with planar transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional lithographic fin spacing is used, then manufacturing simplicity is maintained, but device density is limited
Solution Approach 1:
The fin formation process is segmented into multiple stages: forming sacrificial fins, depositing spacers, selectively removing sacrificial fins, and forming final fins. This segmentation enables sub-lithographic pitch and higher density while maintaining manufacturing feasibility through standardized process modules
Solution Approach 2:
Sacrificial fins are formed in advance as placeholders to define the final fin positions. The spacer material is deposited beforehand to establish the minimum pitch constraints. These preliminary structures guide subsequent processing steps to achieve the desired high-density fin configuration
2Quantity of substance
If fin spacing is reduced to increase density, then device density improves, but facet control becomes more difficult
Solution Approach 1:
A spacer layer acts as an intermediary between the sacrificial fin and the final fin structure. This spacer provides a controlled thickness that defines the minimum pitch and ensures uniform fin spacing, thereby maintaining facet control even at reduced pitch dimensions
Solution Approach 2:
The method changes the critical dimension control parameter from lithographic resolution to spacer layer thickness. By controlling the spacer deposition parameters (such as conformal deposition thickness), precise fin spacing and facet control are achieved independent of lithographic limitations
3Quantity of substance
If more fins are integrated to increase density, then device density improves, but integration with planar transistors becomes more complex
Solution Approach 1:
Different regions of the substrate are assigned different fin configurations: regions with sacrificial fins produce high-density fin transistors, while regions without sacrificial fins produce planar transistors. This local differentiation enables mixed technology integration while maintaining manufacturing simplicity through region-specific processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of densely packed semiconductor devices with improved electrical characteristics and efficient integration of fin transistors with planar transistors, achieving higher density and reduced leakage by utilizing the sacrificial SiGe fin process.
Implementation Method 1
Epitaxial silicon is grown on the sides of the SiGe fin
Data Source
AI summary
There is a method for forming a semiconductor device. Portions of a sacrificial layer are removed to expose a first seed layer region. The first seed layer region corresponds to a first semiconductor region, and a remaining portion of the sacrificial layer corresponds to a second semiconductor region. An epitaxial semiconductor material is deposited over the first seed layer region. A capping layer is formed to overlie the epitaxial semiconductor material and the remaining portion of the sacrificial layer. Portions of the capping layer are removed to form a capping structure that overlies a part of the remaining portion of the sacrificial layer. Portions of the sacrificial layer not covered by the capping structure are removed to form a sacrificial structure having sidewalls. Fin structures are formed adjoining the sidewalls by depositing a semiconductor material along the sidewalls. Portions of the capping structure are removed to expose portions of sacrificial layer between adjacent fin structures. Portions of the sacrificial material between the adjacent fin structures are removed.