Sacrificial Spacer Liners for Interconnect Via Alignment
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Solution Overview
Problem
The continued scaling of semiconductor devices poses challenges in fabricating small conductive wiring interconnect networks, particularly in aligning conductive vias with underlying lines due to misalignment issues and RC delay caused by high capacitance and resistance in narrow-pitch interconnects, which traditional dual damascene techniques struggle to address effectively.
Innovation Solution
The implementation of a sacrificial spacer liner aids in aligning top conductive vias with underlying line trenches by protecting against inadvertent removal and maintaining targeted via dimensions, even in cases of misalignment, allowing for improved overlay and alignment of conductive vias with conductive lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional dual damascene techniques are used to fabricate narrow-pitch interconnects, then manufacturing process simplicity is maintained, but misalignment between conductive vias and underlying lines occurs and RC delay increases due to high capacitance and resistance
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial spacer liner on the sidewalls of the trench before filling it with conductive material. This spacer liner is deposited in advance to define the precise location where the conductive via will be formed, ensuring accurate alignment with the underlying conductive line before the actual via formation occurs. The spacer acts as a pre-positioned alignment reference that guides subsequent processing steps.
Solution Approach 2:
The sacrificial spacer liner serves as an intermediary element between the trench structure and the final conductive via. It mediates the alignment process by providing a physical structure that defines the via location, allowing precise positioning without requiring direct alignment between lithographic patterns. The spacer is temporarily introduced, performs its alignment function, and is later removed after serving its purpose.
2Manufacturing precision
If conductive vias are formed directly in trenches without sacrificial spacers, then fabrication process is simpler, but via critical dimension control and overlay tolerance deteriorate
Solution Approach 1:
The sacrificial spacer liner is formed in advance on the trench sidewalls to define the via location and dimensions. This preliminary structure establishes the precise critical dimensions of the via before conductive material is deposited, ensuring consistent via width and depth control. The spacer acts as a template that guides the subsequent via formation process.
Solution Approach 2:
The patent utilizes parameter changes by controlling the thickness and material properties of the sacrificial spacer liner to precisely define the via critical dimensions. By adjusting the spacer liner thickness through controlled deposition processes, the via width and other dimensional parameters can be precisely tuned to meet design specifications, achieving better CD control than direct trench filling methods.
3Productivity
If narrow-pitch interconnects are fabricated to increase circuit density, then productivity is improved, but RC delay increases due to high capacitance and resistance
Solution Approach 1:
The patent applies local quality by using different materials with optimized properties in different regions of the interconnect structure. The sacrificial spacer liner is made of a specific material with controlled dielectric properties, and the conductive via material is selected for low resistance. This local optimization of material properties helps reduce RC delay while maintaining narrow pitch for high density.
Solution Approach 2:
The interconnect structure employs composite materials comprising the sacrificial spacer liner material and the conductive via material. This composite structure allows optimization of electrical properties (low resistance and capacitance) while maintaining the narrow pitch geometry. The combination of materials with complementary properties enables high-density interconnects with reduced RC delay.
Data Source
AI summary
A method of fabricating an integrated circuit includes forming a first trench such that a portion of the first trench is defined by a portion of a first-type of interconnect and depositing a sacrificial spacer liner in the first trench to cover the portion of the first-type of interconnect element. The method further includes forming a dielectric cap on the sacrificial spacer liner and above the first-type of interconnect element, removing the dielectric cap to expose at least a portion of the first-type of interconnect element, and forming a second-type of interconnect element on the exposed first-type of interconnect element.