Sacrificial Spacer Removal for Stress-Inducing Layer Formation
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling MOSFETs due to shrinking spacings between adjacent gate structures, leading to issues with pre-metal dielectric gap-fill, strain-induced layer deposition, and contact masking and etching, where conventional spacer removal damages underlying silicon and silicide layers.
Innovation Solution
An integrated circuit system employing sacrificial spacers made from materials like amorphous carbon or thermally decomposable materials, which can be removed without damaging the substrate, allowing for the formation of stress-inducing layers to enhance carrier mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional spacer removal processes are used, then the spacer can be removed to enable subsequent processing, but the underlying silicon and silicide layers are damaged
Solution Approach 1:
The patent introduces a sacrificial spacer material that serves as an intermediary layer between the conventional spacer and the underlying silicon/silicide layers. This sacrificial material can be selectively removed through etch processes without damaging the sensitive underlying layers, as it is designed to be more easily etched away. The sacrificial spacer acts as a protective mediator that enables spacer removal while preserving the integrity of the underlying structures.
Solution Approach 2:
The patent employs a disposable sacrificial spacer material that is intentionally designed to be temporary and removable. This sacrificial material is deposited over the conventional spacer, performs its function during critical processing steps (such as preventing stress-induced layer deposition in unwanted areas), and then is completely removed. The underlying spacer and structures remain intact, while the sacrificial material is discarded after serving its purpose.
2Area of stationary object
If spacing between adjacent gate structures is reduced to increase packing density, then device packing density improves, but pre-metal dielectric gap-fill and strain-induced layer deposition become problematic
Solution Approach 1:
The sacrificial spacer material serves as an intermediary that temporarily maintains appropriate spacing between adjacent gate structures during the pre-metal dielectric deposition process. By controlling the thickness and placement of the sacrificial spacer, the patent ensures adequate gap space for proper dielectric gap-fill, even when the final device spacing is reduced for higher packing density. The sacrificial material is later removed to achieve the final compact structure.
3Area of stationary object
If spacing between adjacent gate structures is reduced to increase packing density, then device packing density improves, but contact masking and etching become problematic
Solution Approach 1:
The sacrificial spacer material acts as a protective intermediary during contact masking and etching processes. It temporarily maintains the spacing between structures, providing adequate room for contact formation and etching operations. This allows contact masking and etching to be performed successfully even when the final device spacing is reduced for higher packing density. After contacts are formed, the sacrificial material is removed to achieve the final compact structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the removal of spacers without damaging underlying layers, improving device performance by increasing dense area spacing and enhancing step coverage of stress-inducing layers, thereby reducing variations in device performance and manufacturing costs.
Implementation Method 1
removing the second spacer without damaging the substrate
Implementation Method 2
removal of the disposable spacer causes damage to underlying silicon and silicide layer due to required etch processes
Implementation Method 3
forming a fourth dielectric layer over the integrated circuit system that promotes stress within the channel of the first device, the second device, or a combination thereof
Data Source
AI summary
An integrated circuit system that includes: providing a substrate including a first device and a second device; configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made from a sacrificial spacer material; forming a second dielectric layer over the integrated circuit system; forming a first device source/drain and a second device source/drain adjacent the second spacer and through the second dielectric layer; removing the second spacer without damaging the substrate; forming a third dielectric layer over the integrated circuit system before annealing; and forming a fourth dielectric layer over the integrated circuit system that promotes stress within the channel of the first device, the second device, or a combination thereof.