Sacrificial Layer Via Formation for Aligned Semiconductor Interconnects
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Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, challenges arise in forming metal lines and metal vias in dielectric layers, including misalignment, increased resistance-capacitance (RC) delay, electromigration (EM) reliability issues, time-dependent dielectric breakdown (TDDB), and device defects.
Innovation Solution
The method involves selectively depositing a sacrificial material over underlying metal lines, followed by the deposition of dielectric materials and etching to form recesses exposing the sacrificial material. The sacrificial material is then removed, and metal vias are formed, using selective processes to ensure maximum contact between metal vias and metal lines, reducing misalignment and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional metal line and via formation processes are used, then manufacturing is simpler, but misalignment and device defects increase
Solution Approach 1:
A sacrificial material layer is deposited over the metal lines before forming the dielectric layers and metal vias. This preliminary placement of the sacrificial material establishes a precise spatial reference that guides subsequent etching processes, ensuring metal vias are formed at correct locations with maximum contact to metal lines.
Solution Approach 2:
The sacrificial material acts as an intermediary element between the metal lines and the metal vias. It is temporarily introduced to define the via locations, facilitates precise via formation through selective etching, and is subsequently removed after serving its guiding function, leaving clean via openings with optimal alignment.
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components are integrated into given area, but RC delay and electromigration reliability issues increase
Solution Approach 1:
The sacrificial material is deposited in advance at precise locations corresponding to desired via positions. This preliminary action ensures that even as feature sizes are reduced, the via locations are accurately predetermined, maintaining optimal contact with metal lines and minimizing RC delay and electromigration effects despite smaller dimensions.
Solution Approach 2:
The invention replaces traditional mechanical alignment methods with a chemical field-based approach. The sacrificial material creates a chemical template that guides etching processes, substituting physical alignment mechanisms with field-based self-alignment, thereby achieving superior precision at reduced feature sizes.
3Manufacturing precision
If selective deposition processes are used to ensure maximum contact between metal vias and metal lines, then alignment improves, but manufacturing complexity increases
Solution Approach 1:
The sacrificial material serves as a mediator that simplifies the selective deposition process. By providing a physical and chemical template, it guides subsequent etching operations to automatically align with metal lines, converting a complex alignment problem into a straightforward etching process that follows the sacrificial material's predefined pattern.
Solution Approach 2:
The sacrificial material structure is designed to self-align with the metal lines through the etching process. The selective etching automatically follows the sacrificial material's geometry, creating via openings that naturally achieve maximum contact with metal lines without requiring additional alignment adjustments or complex process controls.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces RC delay, EM reliability issues, TDDB, and device defects, while improving the alignment of metal vias with metal lines, leading to enhanced performance and reliability of semiconductor devices.
Implementation Method 1
selectively depositing a sacrificial material over underlying metal lines
Implementation Method 2
selectively depositing a sacrificial material over underlying metal lines
Implementation Method 3
etching to form recesses exposing the sacrificial material
Data Source
AI summary
An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes forming a metal line extending through a first dielectric layer, the metal line being electrically coupled to a transistor; selectively depositing a sacrificial material over the metal line; selectively depositing a first dielectric material over the first dielectric layer and adjacent to the sacrificial material; selectively depositing a second dielectric material over the first dielectric material; removing the sacrificial material to form a first recess exposing the metal line; and forming a metal via in the first recess and electrically coupled to the metal line.