Buried Power Rail Integration Using Sacrificial Via Plugs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The alignment between buried power rails and vias in integrated circuit devices remains a challenge due to wafer deformation, and existing methods for forming buried power rails and connecting vias are complex and manufacturing-intensive.
Innovation Solution
A method that involves forming a semiconductor device on the frontside of a substrate, including shallow trench isolation structures and a sacrificial plug, followed by backside processing to self-align buried power rails with vias, decoupling active device formation from backside wiring and preventing electrical coupling with the liner covering the separating portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buried power rails are formed during frontside processing, then power delivery is achieved, but metal contamination risk increases during active device formation
Solution Approach 1:
The processing is divided into separate frontside and backside operations. Frontside processing completes active device formation first, then the substrate is flipped and bonded to a carrier wafer. Backside processing forms the buried power rails after frontside processing is complete, eliminating metal contamination risk to active devices while maintaining processing organization.
Solution Approach 2:
The conventional sequence is inverted: instead of forming buried power rails during frontside processing before active devices, the patent forms active devices first on the frontside, flips the substrate, and then forms buried power rails on the backside. This reverse sequencing eliminates contamination risk while achieving the same power delivery function.
2Manufacturing precision
If traditional methods are used to form buried power rails and vias, then power delivery is achieved, but alignment precision deteriorates due to wafer deformation
Solution Approach 1:
Via holes are formed and filled with sacrificial plugs during frontside processing before the substrate is flipped. The sacrificial plugs remain in place during backside processing, serving as pre-positioned alignment references for forming buried power rails, thereby achieving precise alignment without requiring complex alignment procedures after wafer deformation occurs.
Solution Approach 2:
Sacrificial plugs are introduced as intermediary elements that facilitate alignment. These plugs are formed during frontside processing and remain in the via holes during backside processing, serving as physical references that guide the formation of buried power rails with precise alignment, eliminating the need for complex alignment procedures despite wafer deformation.
3Productivity
If active device formation and backside wiring are performed simultaneously, then manufacturing time is reduced, but metal contamination risk increases
Solution Approach 1:
The manufacturing process is segmented into distinct frontside and backside phases. Frontside processing completes active device formation and via formation first. The substrate is then flipped and bonded to a carrier wafer, creating a clear separation. Backside processing forms buried power rails in a subsequent phase, eliminating metal contamination risk while maintaining efficient processing through clear phase separation.
Solution Approach 2:
The potentially contaminating buried power rail formation step is extracted from the frontside processing sequence and relocated to backside processing. This extraction removes the source of metal contamination from the active device formation environment while the substrate flip and carrier wafer bonding maintain manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables self-aligned buried power rails, reduces manufacturing complexity, and mitigates metal contamination risks during active device formation, while allowing for independent frontside and backside processing.
Implementation Method 1
removing the sacrificial plug selectively with respect to the liner, thereby exposing the source or drain contact of the first active device
Implementation Method 2
anisotropically etching the liner so as to expose a first end of the sacrificial plug, while retaining at least part of the liner in the separating portions
Implementation Method 3
providing an electrically conductive material in the via, electrically contacting the source or drain contact of the first active device
Data Source
Figure 1~3
Figure 4~5B
Figure 6A~6C
AI summary
Method for forming an integrated circuit device (98), comprising: a. forming (901) a semiconductor device on a frontside (11) of a substrate (1) comprising: a device layer (2) on the frontside (11) of the substrate (1), the device layer (2) comprising a first active device (20), the substrate (1) comprising: shallow trench isolation structures (139, 131, 132, 133), wherein adjacent shallow trench isolation structures (139, 131, 132, 133) are separated from each other by a separating portion (1391, 1312, 1323) comprising the substrate material (100), a via (130) filled with a sacrificial plug (4) extending through the substrate material (100) in a first separating portion (1312), and wherein the sacrificial plug (4) contacts a source or drain contact (21) of the first active device (20), b. removing (902) the substrate material (100) from a backside of the substrate (1), c. depositing (903) a liner (9) covering the backside (10) of the substrate (1), d. anisotropically etching (904) the liner (9) so as to expose a first end (41) of the sacrificial plug (4), while retaining at least part of the liner (9) in the separating portions (1391, 1312, 1323), e. removing (905) the sacrificial plug (4) selectively with respect to the liner (9), and f. providing (906) an electrically conductive material (30) in the via (130), electrically coupled to a buried power rail (31, 32).