Sacrificial Wafer Substrate for Panel-Level IC Packaging

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Solution Overview

Problem

Existing packaging techniques for integrated circuits, such as leadless leadframe packages, face limitations in efficiency and scalability, particularly in achieving smaller footprints and higher throughput while maintaining thermal performance and cost-effectiveness.

Innovation Solution

The use of a sacrificial semiconductor wafer as a substrate, metallized to create device areas with isolated contacts and die attach pads, allowing for panel-level packaging of integrated circuit dice, followed by encapsulation and subsequent sacrifice of the wafer to expose contacts for external connections, enabling thinner packages and improved thermal performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional leadframes with tie bars and supporting structures are used, then structural support and reliability are improved, but package footprint and thickness increase

Engineering Contradiction:

Improvestructural supportVSAvoidpackage footprint

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent removes the sacrificial semiconductor wafer after die attachment, extracting the supporting structure only when no longer needed. This eliminates the need for permanent tie bars and supporting structures, reducing package footprint while maintaining structural integrity during the packaging process

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The semiconductor wafer serves as a preliminary supporting substrate that provides structural support during die attachment and packaging operations. Once its support function is complete, it is removed, leaving a compact package without permanent supporting structures

Inventive Principle:

Principle #10Preliminary action

2Ease of manufacture

If conventional packaging processes are used, then ease of manufacture is improved, but productivity and throughput are limited

Engineering Contradiction:

Improvemanufacturing process simplicityVSAvoidpackaging throughput

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The patent combines multiple packaging operations into a single panel-level process. Multiple dice are attached to a semiconductor wafer substrate simultaneously, and subsequent steps like wire bonding and encapsulation are performed on the entire panel at once, dramatically increasing throughput compared to individual device packaging

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The semiconductor wafer serves multiple functions: it provides a flat substrate for die attachment, acts as a support structure during packaging, enables panel-level processing, and serves as a sacrificial element that is removed later. This multi-functionality streamlines the manufacturing process

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Area of stationary object

If leadless leadframe packages are used, then package footprint is reduced, but thermal performance and cost-effectiveness are compromised

Engineering Contradiction:

Improvepackage footprintVSAvoidthermal performance

Core Design Contradiction:

Area of stationary objectVSTemperature

Solution Approach 1:

The patent uses a disposable sacrificial semiconductor wafer that is removed after serving its purpose. This approach eliminates the need for complex thermal management structures in the final package, achieving compact footprint while improving thermal performance through direct die-to-encapsulant contact

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces costs, enhances thermal performance, and increases throughput by allowing for larger-scale packaging and thinner components, while eliminating the need for supporting structures like tie bars, enabling more efficient production of integrated circuit packages.

Implementation Method 1

the first surface of the substrate is then covered with an encapsulant such that the encapsulant encapsulates the dice, the contacts and the electrical connections such that these structures remain rigidly fixed relative to one another

Methodology Applied

Scientific EffectEncapsulation:

Implementation Method 2

The semiconductor material of the wafer may be sacrificed by any suitable means. In the preferred embodiment, the wafer is background until the contacts are exposed

Methodology Applied

Scientific EffectBackgrounding:

Data Source

PatentUS8030138B1Methods and systems of packaging integrated circuits

Publication Date: 2011.10.04 NAT SEMICON CORP

AI summary

Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts and a die attach area. Dice are mounted onto each device area and electrically connected to the array of contacts. The entire surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including die attach pads, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.