Sacrificial Waveguide Test Structures for Wafer-Level Optical Chip Testing
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Solution Overview
Problem
Testing individual optical chips on a semiconductor wafer is time-consuming and costly after they have been cleaved from the wafer, and existing methods for testing while still in wafer form face challenges with alignment time and the inability to perform full power tests due to the limitations of on-chip photodiodes.
Innovation Solution
Incorporating sacrificial test structures on the wafer that allow for simultaneous testing of multiple optical chips, which are arranged on adjacent chips or a discardable portion, enabling a full range of optical tests and are disabled upon cleaving, including light sources and receivers integrated with waveguides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If optical chips are tested after being cleaved from the wafer, then individual chip testing can be performed, but the testing process becomes time-consuming and costly
Solution Approach 1:
The patent implements preliminary testing of optical chips while they are still coupled to the wafer before cleaving occurs. Test structures are integrated into the wafer-level package, allowing functional testing to be performed in advance. This eliminates the need for time-consuming post-cleavage testing while maintaining reliable individual chip testing capability through the wafer-level test architecture.
2Loss of time
If an optical probe is used to test individual optical chips while in wafer form, then earlier testing is enabled, but considerable alignment time is required and practical difficulties arise
Solution Approach 1:
The patent introduces intermediary test structures that are integrated directly into the wafer-level package, serving as mediators between the optical chips and external test equipment. These test structures include test waveguides, couplers, and detectors that are pre-configured on the wafer, eliminating the need for complex external optical probes and alignment procedures while enabling early testing.
3Reliability
If an on-chip photodiode is used to test the optical chip, then testing while in wafer form is possible, but the photodiode only receives a small proportion of the output light and cannot enable full power tests
Solution Approach 1:
The patent segments the optical testing function by separating the high-power output path from the detection path. Test structures are positioned at strategic locations along the optical path to tap off small portions of light for detection while allowing the majority of light power to pass through to the output. This segmentation enables both full power testing capability and reliable detection using photodiodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes alignment time and allows for comprehensive optical testing of optical chips while still in wafer form, enabling efficient identification and separation of faulty chips during the production process.
Implementation Method 1
sacrificial test structures... integrated with waveguides
Data Source
AI summary
Sacrificial optical test structures are constructed upon a wafer of pre-cleaved optical chips for testing the optical functions of the pre-cleaved optical chips. The sacrificial optical structures are disabled upon the cleaving the optical chips from the wafer and the cleaved optical chips can be used for their desired end functions. The test structures may remain on the cleaved optical chips or they may be discarded.