Saddle Fin Transistor Fabrication Using Multi-Film Hard Mask
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Solution Overview
Problem
The fabrication of saddle type fin transistors faces challenges due to increased final inspection critical dimension (FICD) caused by height differences between active and field regions, leading to difficulties in achieving gate overlap and potential leakage currents, which degrade device characteristics.
Innovation Solution
A method involving the use of multi-film hard mask (MFHM) layers, such as bifunctional or trifunctional hard mask layers, is employed to form a hard mask pattern that can be evenly coated over structures with varying heights, reducing the FICD and preventing short circuit effects during fin etching and gate formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a hard mask pattern is formed over structures with height differences between active and field regions, then the etching process can proceed, but the final inspection critical dimension (FICD) increases due to the height differences
Solution Approach 1:
The hard mask pattern is divided into multiple segments or layers, allowing each segment to conform to the underlying topography independently. This segmentation enables the hard mask to accommodate height differences between active and field regions without compromising the overall pattern integrity or increasing FICD
Solution Approach 2:
The hard mask pattern is designed with locally adapted properties where different regions have different characteristics suited to their specific topographic conditions. Areas over height differences have modified mask properties compared to flat regions, enabling precise etching control while maintaining manufacturing feasibility
2Ease of manufacture
If the FICD increases due to height differences, then gate overlap becomes difficult to achieve, but the etching process can still be performed
Solution Approach 1:
The hard mask pattern is formed with preliminary compensations for expected FICD increases. The mask design anticipates the dimension changes that will occur during etching and pre-adjusts the pattern to ensure that gate overlap requirements are met after the etching process completes
3Ease of manufacture
If height differences between active and field regions are present, then the structure can be formed, but leakage currents and short circuit effects may occur
Solution Approach 1:
The hard mask pattern serves as an intermediary element that mediates between the height-differentiated structures and the subsequent gate formation process. It provides a uniform reference surface that prevents direct electrical interaction between regions with different heights, thereby eliminating leakage paths and short circuit effects while allowing the underlying structure to maintain its height differences
Data Source
AI summary
A method for fabricating a saddle type fin transistor includes: preparing a substrate where a device isolation structure is already formed; forming a hard mask pattern over the substrate, the hard mask pattern including a coating layer obtained through a coating method; and performing an etching process using the hard mask pattern as an etch mask to form a saddle type fin. The hard mask pattern may be formed in a stack structure including an amorphous carbon layer and the coating layer.